Synopsys’ New Circuit Simulation Environment Improves Productivity — for Free

Synopsys’ New Circuit Simulation Environment Improves Productivity — for Free
by Pawan Fangaria on 02-07-2016 at 12:00 pm

When technology advances, complexities increase and data size becomes unmanageable. Fresh thinking and a new environment for automation are needed to provide the required increase in productivity. Specifically in case of circuit simulation of advanced-node analog designs, where precision is paramount and a large number… Read More


Moving with Purpose for Certainty

Moving with Purpose for Certainty
by Pawan Fangaria on 11-01-2015 at 12:00 pm

In 1492 Christopher Columbus sailed from Spain towards west on Atlantic Ocean in search of Asia and Indies. Between his four voyages (1492 – 1502) he discovered many different islands and then what we call Americas. Although he had a compass with him, imagine searching a needle in a haystack. Even with localization of areas and then… Read More


Replacing the British Museum Algorithm

Replacing the British Museum Algorithm
by Paul McLellan on 09-14-2015 at 7:00 am

In principle, one way to address variation is to do simulations at lots of PVT corners. In practice, most of this simulation is wasted since it adds no new information, and even so, important corners will get missed. This is what Sifuei Ku of Microsemi calls the British Museum Algorithm. You walk everywhere. And if you don’t walk to… Read More


Optimizing SRAM IP for Yield and Reliability

Optimizing SRAM IP for Yield and Reliability
by Daniel Payne on 08-31-2015 at 12:00 pm

My IC design career started out with DRAM at Intel, and included SRAM embedded in GPUs, so I recall some common questions that face memory IP designers even today, like:

  • Does reading a bit flip the stored data?
  • Can I write both 0 and 1 into every cell?
  • Will read access times be met?
  • While lowering the supply voltage does the cell data retain?
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Designing for Variation

Designing for Variation
by Paul McLellan on 08-17-2015 at 7:00 am

There is a widespread phenomenon in designing chips that new effects creep up on you. First they are so small you can ignore them. Then you can add a little pessimism to your timing budget or whatever gets affected. But eventually the effects go from second order to first order. You certainly can’t ignore them, and the guard … Read More


Predicting Lifetime of Analog ICs

Predicting Lifetime of Analog ICs
by Pawan Fangaria on 06-22-2015 at 12:30 pm

With the increase of transistors per unit area, high density interconnects and manufacturing variability at lower nodes, the electronic devices have become more vulnerable to failures. The devices that operate under extreme conditions such as automotive devices that operate at high temperatures need to be robust enough to… Read More


Fast Monte Carlo from Infiniscale at DAC

Fast Monte Carlo from Infiniscale at DAC
by Daniel Payne on 06-14-2012 at 10:56 am

Firas Mohamed, President and CEO (Ph.D.) of Infiniscale met with me on Monday at DAC to provide an overview of what EDA software they offer to IC designers at the transistor-level.


Vision – analog flow that Monte Carlo simulation is required, which is thousands of circuit simulations, however the higher the sigma the more… Read More


Solido – Variation Analysis and Design Software for Custom ICs

Solido – Variation Analysis and Design Software for Custom ICs
by Daniel Payne on 08-15-2011 at 7:11 pm

Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More