Tag: modeling

Webinar: Multiphysics Modeling of HBM for 3D Heterogeneous Integration

Webinar: Multiphysics Modeling of HBM for 3D Heterogeneous Integration
by Admin on 01-14-2025 at 3:31 am

Memory access speeds are a performance bottleneck in today’s high- speed AI and HPC semiconductor designs. High Bandwidth Memory (HBM) in a 3D heterogeneous integrated (3DHI) system is the optimal solution to break through this “memory wall.” It can achieve data rates exceeding 1 TB/s, critical for AI and data center applications.

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SPICE Model Generation using Machine Learning

SPICE Model Generation using Machine Learning
by Daniel Payne on 02-05-2017 at 10:00 pm
Categories: EDA, Platform Design Automation

AI and machine learning are two popular buzz words in the high-tech daily news, so you should be getting used to hearing about them by now. What I hadn’t realized was that EDA companies are starting to use machine learning techniques, and specifically targeted at the daunting and compute intensive task of creating SPICE models… Read More

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Getting out of DIY Mode for Virtual Prototypes

Getting out of DIY Mode for Virtual Prototypes
by Don Dingee on 09-26-2016 at 4:00 pm
Categories: Automotive, EDA, IoT, Synopsys

Virtual prototyping has, inexplicably, been largely a DIY thing so far. Tools and models have come from different sources with different approaches, and it has been up to the software development team to do the integration step and cobble together a toolchain and methodology that fits with their development effort.

That integration… Read More

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Lethal data injection a much bigger threat

Lethal data injection a much bigger threat
by Don Dingee on 08-08-2016 at 4:00 pm
Categories: IoT, Security

Watching a spirited debate on Twitter this morning between Tom Peters and some of his followers reminded me of the plot of many spy movies: silently killing an opponent with a lethal injection of some exotic, undetectable poison. We are building in enormous risks in more and more big data systems.… Read More

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A moment of IoT silence before we disrupt

A moment of IoT silence before we disrupt
by Don Dingee on 11-08-2015 at 12:00 pm
Categories: ESD Alliance, Events, IoT, Semiconductor Services

As I sat down in the SEMI Arizona Chapter breakfast meeting a few weeks ago, a moment of semiconductor history flew right before my eyes before the IoT sessions started.

We were seated in the cafeteria of Freescale Building 94 on Elliot Road in Tempe, a place I’d been many times before, except this time may have been the last. NXP is consolidating… Read More

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Automotive MCU code fault-busting with vHIL

Automotive MCU code fault-busting with vHIL
by Don Dingee on 09-30-2015 at 7:00 pm
Categories: Automotive, EDA, Synopsys

With electronic and software content in vehicles skyrocketing, and the expectations for flawless operation getting larger, the need for system-level verification continues to grow. Last month, we looked at a Synopsys methodology for virtual hardware in the loop, or vHIL… Read More

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Simulating to a fault in automotive and more

Simulating to a fault in automotive and more
by Don Dingee on 08-30-2015 at 12:00 pm
Categories: Automotive, EDA, Synopsys

We’re putting the finishing touches on Chapter 9 of our upcoming book on ARM processors in mobile, this chapter looking at the evolution of Qualcomm. One of the things that made Qualcomm go was their innovative use of digital simulation. First, simulation proved out the Viterbi decoder (which Viterbi wasn’t convinced had a lot … Read More

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Testing Ethernet with virtual co-modeling

Testing Ethernet with virtual co-modeling
by Don Dingee on 08-24-2015 at 12:00 pm
Categories: EDA, Siemens EDA

Ethernet is suddenly a hot topic in SoC design again. The biggest news may be this: it’s not just the cloud and enterprise networks. Those are still important applications. The cloud is driving hard for more ports at 25G server and 100G switch speeds according to a recent Dell’Oro Group report. Enterprise networks are driving for… Read More

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DDR stands for Don’t Do (Just) RTL

DDR stands for Don’t Do (Just) RTL
by Don Dingee on 06-16-2015 at 9:00 pm
Categories: EDA, Synopsys

In optimizing SoC design for performance, there is so much focus on how fast a CPU core is, or a GPU core, or peripherals, or even the efficiency of the chip-level interconnect. Most designers also understand selecting high performance memory at a cost sweet spot, and optimizing physical layout to clock it as fast as possible within… Read More

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A Brief History of ASTC and VLAB Works

A Brief History of ASTC and VLAB Works
by Paul McLellan on 10-24-2014 at 4:00 pm
Categories: EDA

When I worked for VaST our engineering was in Sydney Australia. To my surprise there was another, entirely independent, group working on virtual platform modeling and tools in another place in Australia, in Adelaide. Is there something in the Fosters? They had originally been part of Motorola Corporate R&D and Software Group,… Read More