Scan the horizon, P1687 takes us higher

Scan the horizon, P1687 takes us higher
by Don Dingee on 07-31-2013 at 6:00 pm

The tech standards cycle almost always goes like this: Problems or limits develop with the existing way of doing things. Innovators attempt to engineer solutions, usually many of them. Chaos ensues when customers figure out nothing new works with anything else. Competitors sit down and agree on a specification where things work… Read More


DAC lunch seminar: Better IP Test with IEEE P1687

DAC lunch seminar: Better IP Test with IEEE P1687
by Beth Martin on 05-30-2013 at 7:28 pm

What: DAC lunch seminar (register here)
When: June 5, 2013, 11:30am – 1:30pm
Where: At DAC in lovely Austin, TX

Dr. Martin Keim of Mentor Graphics will present this overview of the new the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG.

If you are involved in IC test*, you’ve probably heard about IJTAG. If you … Read More


IJTAG for IP Test: a free seminar

IJTAG for IP Test: a free seminar
by Beth Martin on 03-14-2013 at 1:53 pm

What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538


If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More


Mentor and NXP Demonstrate that IJTAG Can Reduce Test Setup Time for Complex SoCs

Mentor and NXP Demonstrate that IJTAG Can Reduce Test Setup Time for Complex SoCs
by glforte on 11-15-2012 at 8:10 pm

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, a new IEEE P1687 standard is being defined by a broad coalition of IP vendors, IP users, major ATE companies, and all three major EDA vendors. This new standard, also called… Read More


IJTAG, Testing Large SoCs

IJTAG, Testing Large SoCs
by Paul McLellan on 11-08-2012 at 5:57 pm

Test is the Rodney Dangerfield of EDA, it doesn’t get any respect. All designs need to be tested but somehow synthesis, routing, analog layout and the rest are the sexy areas. In my spoof all purpose EDA keynote address I even dissed it:You are short on time so slip in a quick mention of manufacturing test. Who knows anything … Read More