The challenges of 7nm are well documented. Lithography artifacts create exploding design rule complexity, mask costs and cycle time. Noise and crosstalk get harder to deal with, as does timing closure. The types of applications that demand 7nm performance will often introduce HBM memory stacks and 2.5D packaging, and that creates… Read More
I have previously published analysis’ converting leading edge logic processes to “standard nodes” and comparing standard nodes by company and time. Recently updated details on the 7nm process node have become available and in this article, I will revisit the standard node calculations and trends.… Read More
Scott Jones and I had the opportunity to talk again with Gary Patton, GlobalFoundries CTO and SVP of R&D for a quick update on 7nm and EUV. Gary has been at GF for two years now with more than 500 other technologists from the IBM semiconductor acquisition. 7nm is the first IBM based process from GF (14nm was licensed from Samsung),… Read More
Word on the street is that TSMC is on schedule with 16FFC, 10nm and 7nm, which is a very big deal for the fabless semiconductor ecosystem. As Scotten Jones has illustrated in the graphic below, for the first time in the history of the semiconductor industry a pure-play foundry (TSMC) will have the process lead over Intel. And this is… Read More
