Software defined networks were a technique developed around 6 years ago. The original structure of IP based network scaled by using additional routers that would forward packets based on partial information about the network topology. Inside each router was a dataplane, where the packets themselves flowed through, and a control… Read More
Tag: fpga
Living with DO-254? You need Aldec!
I will say that as popular as DO-254 and the like is, I am not the fella for that. It can take the simplest of designs into a realm of test and verification like you have never seen before. Yes, when I am flying I happen to be a big fan of this rigorous testing but you will not find me doing that job anytime soon. While the topic is very dry, it … Read More
Xilinx Quarterly Results: 20nm Prototypes
Xilinx announced their quarterly results last week. Because of their financial year not being aligned with their calendar year this is actually 4th quarter of their 2014 financial year. New Year’s Eve 2015 comes early for Xilinx. The results were very good. As Moshe Gavrielov, the CEO, said on the conference call:Xilinx… Read More
Xilinx Showcases Worlds First ‘High Performance’ Analogue FPGA
Last February Xilinx presented a prototype device at the 2014 IEEE international Solid-State Circuits Conference (ISSCC, titled “A Heterogeneous 3D-IC Consisting of Two 28nm FPGA Die and 32 Reconfigurable High-Performance Data Converters” and click here to get a copy of the paper. Let me just share the intro my dear reader… … Read More
Aldec the leader in DO254
I am convinced after studying out the matter, that Aldec is one of the leaders in DO254 certification. As you listen and read the news as I do about flight MA-370, you keep theorizing and wondering. This is a good time to introduce the reader to the seriousness of flight worthy electronics and the arduous process to achieve certification.… Read More
Xilinx & Apache Team up for FPGA Reliability at 20nm
In this age of SoCs with hundreds of IPs from different sources integrated together and working at high operating frequencies, FPGA designers are hard pressed keeping up the chip reliability from issues arising out of excessive static & dynamic IR drop, power & ground noise, electro migration and so on. While the IPs are… Read More
Xilinx: Delivering a Generation Ahead
Last week was Xilinx’s investor day. Xilinx believe they are now a process generation ahead. They did over $100M in 28nm designs in FY2013 (Xilinx FY ended March 2013) and did over over $100M in Q4 2013 calendar year alone (and this is almost all true production volume, with only about 5% prototypes) with a plan greater than … Read More
I switched to Aldec Active-HDL
I have written this before, but I was a ModelSim snob. That has changed after trying Active-HDL from Aldec. I have no plans on going back to ModelSim. You ask why? Well astute reader, great question. Unfortunately these blogs are text limited and there is no way to write about all the bells and whistles of Active-HDL. So before I continue,… Read More
Have you Tried ALDEC?
I must admit. I was too comfortable. Let me explain, I’m a ModelSim guy from Mentor Graphics. I did not really think nor care much of the other RTL simulator options. How could someone build a better tool with respect to simulation? Let me introduce you to Aldec. Aldec was founded in 1984 by Dr. Stanley M. Hyduke. 30 years later they are… Read More
Structured Asic Dies…Again
There has always been a dream that you could do a design in a cheap easy to design technology and then, if the design was a hit, press a button and instantly move it into a cheaper unit-price high volume design. When I was at VLSI in the 1980s we had approaches to make it easy to move gate arrays (relatively large die area) into standard cells… Read More