Cache Coherent Systems Get a Boost from New Technology

Cache Coherent Systems Get a Boost from New Technology
by Tom Simon on 05-20-2016 at 12:00 pm

The speed and power penalties for accessing system RAM affect everything from artificial intelligence platforms to IoT sensor nodes. There is a huge power and performance overhead when the various IP blocks in an SOC need to go to DRAM. Memory caches have become essential to SOC design to reduce these adverse effects. However, … Read More


Enterprise SSD SOC’s Call for a Different Interconnect Approach

Enterprise SSD SOC’s Call for a Different Interconnect Approach
by Tom Simon on 03-01-2016 at 12:00 pm

The move to SSD storage for enterprise use brings with it the need for difficult to design enterprise capable SSD controller SOC’s. The benefits of SSD in hyperscale data centers are clear. SSD’s offer higher reliability due to the elimination of moving parts. They have a smaller foot print, use less power and offer much better performance.… Read More


Nine Cost Considerations to Keep IP Relevant

Nine Cost Considerations to Keep IP Relevant
by Pawan Fangaria on 09-27-2015 at 12:00 pm

It’s about 15 years the concept of IP development and its usage took place. In the recent past the semiconductor industry witnessed start of a large number of IP companies across the globe. However, according to Gary Smith’s presentation before the start of 52[SUP]nd[/SUP] DAC, IP business is expected to remain stagnant for next… Read More


SSD Storage Chips: Basic Interconnect Considerations

SSD Storage Chips: Basic Interconnect Considerations
by Majeed Ahmad on 07-31-2015 at 4:00 pm

The joint development of 3D XPoint memory technology from Intel and Micron has once more brought the spotlight on data centers and chips for solid-state drives (SSDs). The two semiconductor industry giants claim that 3D XPoint memory is1,000 times faster than NAND Flash: the underlying memory content for SSDs. Such developments… Read More


Is Interconnect Ready for the Post-mobile SoCs?

Is Interconnect Ready for the Post-mobile SoCs?
by Majeed Ahmad on 06-28-2015 at 2:00 pm

The interconnect technology is one of the unsung heroes of the system-on-chip (SoC) revolution. It’s the on-chip networking fabric that is used to link various IP cores on an SoC floorplan. The technology facilitates links between multiple processors, on-chip memories, hardware accelerators and more. In other words,… Read More


Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design

Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design
by Majeed Ahmad on 04-19-2015 at 9:00 am

China was a virgin territory for Arteris Inc. before July 19, 2012 when Fuzhou Rockchip Electronics announced that it has licensed the Arteris FlexNoC network-on-chip (NoC)-based interconnect IP technology for its multicore SoCs for budget Android tablets. Rockchip mostly targets the tablet and set-top box (STB) markets … Read More


SoCs in New Context Look beyond PPA

SoCs in New Context Look beyond PPA
by Pawan Fangaria on 03-21-2015 at 7:00 am

If we look back in the last century, performance and area were two main criteria for semiconductor chip design. All design tools and flows were concentrated towards optimizing those two aspects. As a result, density of chips started increasing and power became a critical factor. Now, Power, Performance and Area (PPA) are looked… Read More


Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip

Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip
by Majeed Ahmad on 03-14-2015 at 7:00 am

Arteris Inc., a network-on-chip (NoC) interconnect IP solution provider, has joined hands with Texas Instruments Inc. to create an ultra-low-power chip that helps Internet of Things (IoT) devices go battery-less with energy harvesting and support coin cell-powered IoT operation for multiple years.

Another low-power MCU… Read More


Arteris on a winning streak in 2014

Arteris on a winning streak in 2014
by Don Dingee on 11-19-2014 at 3:00 am

When Arteris sold key network-on-chip intellectual property and most of its human assets to Qualcomm earlier this year, it was big news. We suggested the bigger news after a restaffing effort would be a next-generation NoC release, and a new round of design wins.

Some developments were already in the pipeline. … Read More


Taming The Interconnect In Real World For SoCs

Taming The Interconnect In Real World For SoCs
by Pawan Fangaria on 12-13-2013 at 1:30 pm

Interconnect plays a significant role in the semiconductor design of a SoC; if not architected and handled well, it can lead to an overdesigned SoC impacting on its power, performance and area. Since a SoC generally contains multiple IPs requiring different data paths to satisfy varying latency and performance cycles, it has … Read More