Revisiting EUV Lithography: Post-Blur Stochastic Distributions

Revisiting EUV Lithography: Post-Blur Stochastic Distributions
by Fred Chen on 11-14-2021 at 10:00 am

Revisiting EUV Lithography Post Blur Stochastic Distributions

In previous articles, I had looked at EUV stochastic behavior [1-2], primarily in terms of the low photon density resulting in shot noise, described by the Poisson distribution [3]. The role of blur to help combat the randomness of EUV photon absorption and secondary electron generation and migration was also recently considered… Read More


Stochastic Effects from Photon Distribution Entropy in High-k1 EUV Lithography

Stochastic Effects from Photon Distribution Entropy in High-k1 EUV Lithography
by Fred Chen on 08-04-2021 at 10:00 am

Stochastic Effects from Photon Distribution Entropy in High k1 EUV Lithography

Recent advances in EUV lithography have largely focused on “low-k1” imaging, i.e., features with pitches less than the wavelength divided by the numerical aperture (k1<0.5). With a nominal wavelength of 13.5 nm and a numerical aperture of 0.33, this means sub-40 nm pitches. It is naturally expected that larger… Read More


CD-Pitch Combinations Disfavored by EUV Stochastics

CD-Pitch Combinations Disfavored by EUV Stochastics
by Fred Chen on 11-29-2020 at 6:00 am

CD Pitch Combinations Disfavored by EUV Stochastics

Ongoing investigations of EUV stochastics [1-3] have allowed us to map combinations of critical dimension (CD) and pitch which are expected to pose a severe risk of stochastic defects impacting the use of EUV lithography. Figure 1 shows a typical set of contours of fixed PNOK (i.e., the probability of a feature being Not OK due… Read More


Application-Specific Lithography: 20nm Flash, 3D XPoint, 3D NAND Bit Lines

Application-Specific Lithography: 20nm Flash, 3D XPoint, 3D NAND Bit Lines
by Fred Chen on 08-10-2020 at 6:00 am

Application Specific Lithography SemiWiki

Nonvolatile memory capacity reached 64 Gb levels when NAND Flash half-pitch reached 20 nm [1]. Having reached 14 nm [2], NAND Flash half-pitch is no longer being reduced, now that it has entered the 3D era. However, recently, 3D XPoint has found applications within the Optane platform [3]. The lithography for patterning 20 nm half-pitch… Read More


Online Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)

Online Class: Advanced CMOS Technology 2020 (The 10/7/5 NM Nodes)
by Daniel Nenni on 04-12-2020 at 9:00 am

3D Finet Model

Our friends at Threshold Systems have a new ONLINE class that may be of interest to you. It’s an updated version of the Advanced CMOS Technology class held last February. This is normally a classroom affair but to accommodate the recent COVID-19 travel restrictions it is being offered virtually.

As part of the previous class we did… Read More


TSMC Update Q3 2019 Absolutely!

TSMC Update Q3 2019 Absolutely!
by Daniel Nenni on 10-25-2019 at 6:00 am

This will be a combination of the recent TSMC quarterly report, a look back at Cliff Hou’s keynote at the most recent TSMC conference, and conversations on SemiWiki.com. There has been a lot of press on this but of course the most important points are being missed. Semiconductors are complicated and getting more so, absolutely.… Read More


Semiconductor Metrology Inspection Outpacing Overall Equipment Market in 2018

Semiconductor Metrology Inspection Outpacing Overall Equipment Market in 2018
by Robert Castellano on 12-31-2018 at 7:00 am

As uncertainties mount about the near-term semiconductor industry from companies in Apple’s supply chain and the significant drop in memory chip prices, the semiconductor industry has consistently grown each year since the great recession of 2009. Semiconductor revenues have consistently outpaced semiconductor equipment… Read More


The Latest from Samsung Semiconductor

The Latest from Samsung Semiconductor
by Tom Dillinger on 10-29-2018 at 12:00 pm

Earlier this Spring, Samsung Foundry held a technology forum, describing their process roadmap and supporting ecosystem developments (link). Recently, the larger Samsung Semiconductor organization conducted a Tech Day at their campus in San Jose, presenting (and demo-ing) a broader set of products. The focus of the day was… Read More