It’s been the case most of the time that until we hit a bottleneck situation, we do not realize that our focus is not at the right spot. Similar is the case with power analysis at the SoC level. Power has become equally if not more important than the functionality and other parameters of an SoC, and therefore has to be verified earlier … Read More
Last month in DAC I could see some of the top innovations in the EDA world. EDA is a key enabler for advances in semiconductor designs. Among a number of innovations worth mentioning (about which I blogged just after DAC), the integration of Mentor’s Veloce with ANSYS’ PowerArtist for power analysis of live applications caught my… Read More
As the number of CPU, GPU, and IP is growing in an SoC, power management is becoming more and more a complex task in itself. A single tool or methodology may not be enough for complete power management and verification of an SoC. In an SoC, there can be multiple modes of operations involving hardware and software interactions, different… Read More
Synopsys had their earnings announcement and call last week. They were good. In Aart’s own words:I’m happy to report that our second quarter results were very strong and solidify our outlook for the full year. We delivered revenue of $557 million, non-GAAP earnings per share of $0.68 and $155 million in operation cash flow.… Read More
It’s less than four weeks to go at DAC 2015 and the program is final now. So I started investigating new technologies, trends, methodologies, and tools that will be unveiled and discussed in this DAC. In the hindsight of the semiconductor industry over the last year, I see 14nm technologies in the realization stage and 10nm beckoning… Read More
Mentor Graphics’ User2User conference will be held next week on April 21[SUP]st[/SUP] at the San Jose DoubleTree Hotel. This one-day, free conference is the perfect opportunity to learn, network, and share with other Mentor Graphics users.
The day starts off with back-to-back keynotes that examine different aspects of the … Read More
Yesterday Mentor announced their quarterly results. Since their financial year is not aligned with the calendar year, this was also the end of their fiscal 2015. The quarter was an all-time record with revenues of $439M and (non-GAAP) EPS of $1.09. The year was also an all-time record with revenues of $1.24B and EPS of $1.77. Half… Read More
Using an assertion is a sure shot method to detect an error at its source, which may be buried deep within a design. It does not depend on a test bench or checker, and can fire automatically as soon as a violation occurs. However, writing assertions manually is very difficult and time consuming. To do so require deep design and coding… Read More
Amid burgeoning complexity of SoC verification with ever increasing hardware, software and firmware content, verification engineers are hard pressed with learning multiple tools, technologies and methodologies and still completing SoC verification with full accuracy in time. The complexity, size and diversity of SoC … Read More
Chip deadlines and the time to achieve sufficient verification coverage run continuously in a tight loop like a dog chasing its tail. Naturally it is exciting when innovative technologies can be combined so that verification can gain an advantage. Software based design simulators have been the mainstay of verification methodologies.… Read More
