Elevating AI with Cutting-Edge HBM4 Technology

Elevating AI with Cutting-Edge HBM4 Technology
by Kalar Rajendiran on 09-30-2024 at 10:00 am

HBM4 Compute Chiplet Subsystem

Artificial intelligence (AI) and machine learning (ML) are evolving at an extraordinary pace, powering advancements across industries. As models grow larger and more sophisticated, they require vast amounts of data to be processed in real-time. This demand puts pressure on the underlying hardware infrastructure, particularly… Read More


Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation

Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation
by akanksha soni on 03-06-2024 at 2:00 pm

Ansys and Intel Foundry Direct 2024

In the dynamic realm of technological innovation, collaborations and partnerships often serve as catalysts for groundbreaking advancements. Continuing along this trajectory, Ansys, a global leader in engineering simulation software, has forged a partnership with Intel Foundry to enable multiphysics chip design. The … Read More


UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem
by Kalar Rajendiran on 12-11-2023 at 6:00 am

Pike Creek UCIe Test chip

Intel recently made headlines when CEO Pat Gelsinger unveiled the world’s first UCIe interoperability test chip demo at Innovation 2023. The test chip built using advanced packaging technology is codenamed Pike Creek and is used to demonstrate interoperability across chiplets designed by Intel and Synopsys. More details … Read More


Intel Enables the Multi-Die Revolution with Packaging Innovation

Intel Enables the Multi-Die Revolution with Packaging Innovation
by Mike Gianfagna on 07-24-2023 at 6:00 am

Intel Enables the Multi Die Revolution with Packaging Innovation

The trend is undeniable. Highly integrated monolithic chips can no longer handle the demands of next-generation systems. The reasons for this significant shift in design are many. Much has been written on the topic; you can get a good overview of the forces at play in multi-die design here. These changes represent the next chapter… Read More


Highlights of the “Intel Accelerated” Roadmap Presentation

Highlights of the “Intel Accelerated” Roadmap Presentation
by Tom Dillinger on 07-30-2021 at 6:00 am

ribbon FETs

Introduction

Intel recently provided a detailed silicon process and advanced packaging technology roadmap presentation, entitled “Intel Accelerated”.  The roadmap timeline extended out to 2024, with discussions of Intel client, data center, and GPU product releases, and especially, the underlying technologies to be … Read More


Intel’s EMIB Packaging Technology – A Deep Dive

Intel’s EMIB Packaging Technology – A Deep Dive
by Tom Dillinger on 05-03-2021 at 6:00 am

EMIB configurations

The evolution of low-cost heterogeneous multi-chip packaging (MCP) has led to significant system-level product innovations.  Three classes of MCP offerings have emerged:

  • wafer-level fan-out redistribution, using reconstituted wafer substrates of molding compound as the surface for interconnections between die (2D)
Read More

The Coming Tsunami in Multi-chip Packaging

The Coming Tsunami in Multi-chip Packaging
by Tom Dillinger on 07-12-2019 at 6:00 am

The pace of Moore’s Law scaling for monolithic integrated circuit density has abated, due to a combination of fundamental technical challenges and financial considerations.  Yet, from an architectural perspective, the diversity in end product requirements continues to grow.  New heterogeneous processing units are being… Read More