The Scariest Graph I’ve Seen Recently

The Scariest Graph I’ve Seen Recently
by Paul McLellan on 07-01-2012 at 4:00 pm

Everyone knows Moore’s Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives… Read More


Chip Synthesis at DAC

Chip Synthesis at DAC
by Paul McLellan on 06-27-2012 at 8:30 pm

I visited Oasys Design Systems and talked to Craig Robbins, their VP sales. For the first time this year, Oasys has a theater presentations and demos of RealTime Designer which are open to anyone attending the show. In previous years, they have had suite demos for appropriately qualified potential customers but outside they have… Read More


TSMC Threater Presentation: Lorentz Solution!

TSMC Threater Presentation: Lorentz Solution!
by Daniel Nenni on 06-26-2012 at 8:30 pm

Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.

TSMC and Lorentz work … Read More


AMS Simulation Update from Mentor Graphics at DAC

AMS Simulation Update from Mentor Graphics at DAC
by Daniel Payne on 06-25-2012 at 12:36 pm

I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.… Read More


TSMC Theater Presentation: Apache

TSMC Theater Presentation: Apache
by Paul McLellan on 06-25-2012 at 12:13 am

At the TSMC Theater Apache (don’t forget, now a subsidary of Ansys) talked about Emerging Challenges for Power, Signal and Reliability Verification on 3D-IC and Silicon Interposer Designs. The more I see about the costs and challenges of 20/22nm and below, the more I think that these 3D and 2.5D approaches are going to be … Read More


EDA Tools to Optimize Memory Design

EDA Tools to Optimize Memory Design
by Daniel Payne on 06-21-2012 at 8:15 pm

I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they’ve expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more… Read More


Mike Muller’s ARM Keynote at DAC 2012

Mike Muller’s ARM Keynote at DAC 2012
by Paul McLellan on 06-21-2012 at 7:30 pm

Mike Muller’s keynote focused on a lot of changes since the ARM1 was designed in 1983 when ARM the company did not exist and ARM was the next generation processor for Acorn Computer, which was really in the hobby market and had its first boost when they had a contract to design the BBC Microcomputer to go along with a computer literacy… Read More


Double Patterning Technology at DAC

Double Patterning Technology at DAC
by Daniel Payne on 06-20-2012 at 5:12 pm

David Abercrombie from Mentor Graphics met with me on Tuesday at DAC to provide an update on DPT – Double Patterning Technology, something new required for several layers starting at the 20nm node in order to get any IC yield. DPT is also part of Multiple-Patterning.… Read More


IPL Alliance at DAC

IPL Alliance at DAC
by Daniel Payne on 06-20-2012 at 3:25 pm

Lunch on Tuesday at DAC was sponsored by the IPL Alliance and thankfully this year they skipped the attempt at humor and focused on interoperable PDKs. Presenting companies include: Synopsys, Dongbu HiTek, TowerJazz, X-FAB and Si2. Having both OpenPDK and iPDK on the same platform does sound like a peaceful co-existence to me,… Read More