GlobalFoundries did a nice response to my “How has 20nm Changed the Semiconductor Ecosystem?” and redefined the word collaboration. Our industry is plagued with sound bites and acronyms so let us agree on a semiconductor ecosystem definition of collaboration.
Mojy Chianis senior vice president, design enablement at… Read More
Electronics markets bounced back strongly in 2010 from the 2008-2009 recession. The recovery stalled in 2011 as a series of natural and human-made disasters hit various parts of the world. Japan was hit by an earthquake and tsunami in March 2011. Thailand was affected by floods which disrupted HDD production and thus impacted … Read More
The press has been buzzing about 3D everything for the past few years, so when it comes to IC design it’s a fair question to ask how would you actually extract 3D IC structures for use by analysis tools like a circuit simulator. I read a white paper by Christen Decoin and Vassilis Kourkoulos of Mentor Graphics this week and became… Read More
EDAC announced that EDA industry revenue increased 6.3% for Q1 2012 to $1536.9M compared to a year ago. Sequentially it declined, as it normally does from Q4 to Q1, by 9.6%. Every category except services increased revenue and every region increased revenue except for Japan. The full report is available by subscription, of course.… Read More
Have you seen the latest design rule manuals? At 28nm and 20nm design sign-off is no longer just DRC and LVS. These basic components of physical verification are being augmented by an expansive set of yield analysis and critical feature identification capabilities, as well as layout enhancements, printability, and performance… Read More
Matt Elmore of ANSYS/Apache has an interesting blog posting about thermal analysis in 3D integrated circuits. With both technical and economic challenges at process nodes as we push below 28nm, increasingly product groups are looking towards through-silicon-via (TSV) based approaches as a way of keeping Moore’s law… Read More
Last month at DAC I learned how IBM, Cadence, ARM, GLOBALFOUNDRIES and Samsung approach the challenges of SoC design, EDA design and fabrication at the 20nm node. Today I followed up by reading a white paper on 20nm IC design challenges authored by Cadence, a welcome relief to the previous marketing mantra of EDA 360.
Here’s… Read More
Over the years many attempts have been made to increase the level of automation in analog design. Most of these have not been especially successful. Probably part of the reason was inadequate technology but also there is an attitude that “real” analog designers design polygons on the bare silicon. I think two things… Read More
There is an interesting Gizmodo review of an HTC Android-based smartphone. The basically positive review (as good as the iPhone, best Android phone at the time) ends up with an update:UPDATE: After more extensive testing there’s something a little weird going on. You’ll probably only see this while gaming, but there’s… Read More
The 1st Atrenta Technology Forum in Japan (well, it used to be the user group meeting, so it’s only the first in a very technical sense) is next week on July 19th from 1pm until 5.15pm. It will be held in the Shin-Yokohama Kokusai Hotel (how to access it here).
In the unlikely event that non-Japanese are reading this blog, here’s… Read More
