Anyone interested in learning about general trade compliance concepts or how export control and sanction regulations affect the electronic systems design ecosystem will want to attend the upcoming ESD Alliance export seminar. It will be hosted by Ada Loo, chair of the ESD Alliance Export Committee and Cadence’s Group Director… Read More
Tag: eda
Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward
You don’t often hear about the inner workings of EDA tools and flows – the marketing guys much prefer telling us about all the exciting things their tools can do rather than the internal plumbing. But this matters for making design flows – and building these has largely been left to the users to sort out. That’s an increasing challenge… Read More
Podcast EP132: The Growing Footprint of Methodics IPLM with Simon Butler
Dan is joined by Simon Butler, the founder and CEO of Methodics Inc, Methodics was acquired by Perforce in 2020, and he is currently the general manager of the Methodics business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to service the needs of IP and component based design.… Read More
Cracking post-route Compliance Checking for High-Speed Serial Links with HyperLynx
SemiWiki readers from a digital IC background might find it surprising that post-PCB route analysis for high speed serial links isn’t a routine and fully automated part of the board design process. For us, the difference between pre- and post-route verification is running a slightly more accurate extraction and adding SI modelling,… Read More
The Role of Clock Gating
Perhaps you’ve heard the term “clock gating” and you’re wondering how it works, or maybe you know what clock gating is and you’re wondering how to best implement it. Either way, this post is for you.
Why Power Matters
I can’t help but laugh when I watch a movie where the main characters are shrunk… Read More
STOP Writing RTL for Registers
After almost three decades in the EDA business, it is beyond my comprehension to understand why chip designers still hand-write RTL for complex register maps – chip designs with hundreds of registers and thousands of register fields. In today’s silicon world where software is the key to chip-based product success, it is the register… Read More
The Increasing Gaps in PLM Systems with Handling Electronics
Product LifeCycle Management (PLM) systems have shown incredible value for integrating the enterprise with a single view of the product design, deployment, maintenance, and end-of-life processes. PLM systems have traditionally grown from the mechanical design space, and this still forms their strength.
Meanwhile, due… Read More
Resilient Supply Chains a Must for Electronic Systems
The last few years have seen multiple disruptions in the supply chain in many industries. One of the key technologies that many fingers have pointed to is the semiconductor technology. As products in all industries become more electronics based, semiconductors play a key role since no end system could function today without … Read More
EDA Product Mix Changes as Hardware-Assisted Verification Gains Momentum
The Design Automation Conference, as always, is a good barometer on the state of EDA and my area of interest, verification. The recent DAC offered plenty of opportunities to check on trends and the status quo.
Remarkably, exhibitors and attendees were upbeat about the chip design landscape despite concerns about supply chain … Read More
An EDA AI Master Class by Synopsys CEO Aart de Geus
I consider Dr. Aart de Geus one of the founding fathers of EDA and one of the most interesting people in the semiconductor industry. So it is not a surprise that Aart was chosen to attend the CHIPs Act signing at the White House.
Here is his current corporate bio:
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys… Read More
