3D Architectures for Semiconductor Integration and Packaging

3D Architectures for Semiconductor Integration and Packaging
by Paul McLellan on 12-10-2012 at 4:00 am

There is obviously a lot going on in 3D IC these days. And I don’t mean at the micro level of FinFETs which is also a way of going vertical. I mean through-silicon-via (TSV) based approaches for either stacking die or putting them on an interposer. Increasingly the question is no longer if this technology will be viable (there… Read More


Double Patterning Verification

Double Patterning Verification
by Paul McLellan on 12-10-2012 at 3:03 am

You can’t have failed to notice that 20nm is coming. There are a huge number of things that are different about 20nm from 28nm, but far and away the biggest is the need for double patterning. You probably know what this is by now, but just in case, here is a quick summary.

Lithography is done using 193nm light. Today we use immersion… Read More


Apache Power Artist Capabilities I

Apache Power Artist Capabilities I
by Paul McLellan on 12-06-2012 at 2:05 pm

I sat down last week with Paul Traynar who was over from UK. He is Apache’s PowerArtist guru. The first thing we talked about was PowerArtist’s sequential power reduction capabilities.

Forward propagation of enables means that when a register is clock gated and feeds a downstream register then that register can be… Read More


A Brief History of the Fabless Semiconductor Ecosystem

A Brief History of the Fabless Semiconductor Ecosystem
by Daniel Nenni on 12-05-2012 at 7:00 pm

Clearly the fabless semiconductor ecosystem is driving the semiconductor industry and is responsible for both the majority of the innovation and the sharp decline in consumer electronics costs we have experienced. By definition, a fabless semiconductor company does not have to spend the time and money on manufacturing related… Read More


Microprocessor Test and Verification 2012

Microprocessor Test and Verification 2012
by Paul McLellan on 12-05-2012 at 5:43 pm

Next week December 10-12th is the Microprocessor Test and Verification (MTV 2012) which is in Austin Texas (as DAC will be next year, of course). After lunch on Monday there is a panel session on the effectiveness of virtual prototyping entitled When simulation suffices, who needs FPGA or emulation? Bill Neifert, the CTO of Carbon… Read More


Formal Analysis of Security Data Paths

Formal Analysis of Security Data Paths
by Paul McLellan on 12-05-2012 at 5:07 pm

One challenge with security in systems is to ensure that there are not backdoors, either accidentally or maliciously inserted. Intel, ARM and others have various forms of trusted execution technology. Under the hood these are implemented by dividing the design into two parts, normal and secure, and implementing them with physical… Read More


Double Patterning Exposed!

Double Patterning Exposed!
by SStalnaker on 12-04-2012 at 7:15 pm

Wanna become the double patterning guru at your company? David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of double patterning,Read More


SystemC vs C++ for High Level Synthesis

SystemC vs C++ for High Level Synthesis
by Paul McLellan on 12-04-2012 at 4:00 pm

One of the decisions that needs to be made when using high-level synthesis (HLS) in general and Catapult in particular is what language to use as input. The choice is C++ or SystemC. Of course at some level SystemC is C++ with added libraries and templates, but in fact the semantics of the two languages end up being very different.

The… Read More


Mixed-Signal Methodology Guide: Design Management

Mixed-Signal Methodology Guide: Design Management
by Daniel Payne on 12-04-2012 at 11:04 am

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I reviewed the book Mixed-Signal Methodology Guidein August of this year published by Cadence, and decided to follow up with one of the authors, Michael Henrie from ClioSoft, to learn more about the importance of Design Management for AMS. Michael is a Software Engineering Manager at ClioSoft and has worked at Zarlink Semi, Legerity,… Read More


Arteris answer to Sonics: should compare actual NoC (in Silicon proven SoC) performance, instead of potential, unproven NoC performances!

Arteris answer to Sonics: should compare actual NoC (in Silicon proven SoC) performance, instead of potential, unproven NoC performances!
by Eric Esteve on 12-02-2012 at 5:06 am

It seems that Ateris vs. Sonics war, initiated by Sonics in 2010 on the legal battle field, is now continuing on the marketing field, as far as I am concerned, I prefer the latter, as I am an engineer and not a lawyer, and I must say that playing in the marketing allow both companies to extract the most attractive features of their products.… Read More