The conference program for DAC is now live here including the conference itself, keynotes, some other special tracks, the pavilion panels and more. And the must-see panel is on emulation at 4pm on Tuesday afternoon moderated by…well, that would be me so I’m a bit biased.
Tag: eda
Mentor at TSMC Technology Symposium
TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, … Read More
TSMC on Collaboration: JIT Ecosystem Development
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry’s Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be … Read More
Will 14nm Yield?
If I had a nickel for every time I heard the term “FinFET” at the 2013 SNUG (Synopsys User Group) Conference I could buy a dozen Venti Carmel Frappuccinos at Starbucks (my daughter’s favorite treat). In the keynote, Aart de Geus said FinFET 14 times and posed the question: Will FinFETs Yield at 14nm? So that was my mission, ask everybody… Read More
Moore Push Versus Market Pull
I was at SNUG earlier today at both Aart’s keynote that opened the conference and at his “meet the press” Q&A just before lunch. The keynote was entitled Bridges to the Gigascale Decade. And the presentation certainly contained lots of photos of bridges! Anyway, I’m going to focus on just one thing,… Read More
New ways for High Frequency Analysis of IC Layouts
Amidst frequently changing requirements, time pressure and demand for high accuracy, it is imperative that EDA and design companies look at time consuming processes in the overall design flow and find alternatives without losing accuracy. High Frequency Analysis of IC designs is one such process which is traditionally based… Read More
A New Mixed-Signal IC Router
Pure digital routers for IC designs have an easier task than mixed-signal routers, because mixed-signal routers have more constraints like:
- Shielded buses
- Differential pairs
- Twisted pairs
- Matched RC routing
- 20nm technology rules
- Double Patterning Technology (DPT)
Can Samsung Deliver As Promised?
Samsung’s aggressive marketing is starting to hit the fabless semiconductor ecosystem so we had all better be prepared. Samsung’s 2012 marketing budget exceeded $400M which probably beats the marketing budget of the entire fabless ecosystem! The question is, will the fabless semiconductor industry be easily swayed by Samsung’s… Read More
Mixed-Signal SoC verification has integrated solution
These days when we talk of SoC verification, what comes to our mind immediately is VirtualPlatform. Of course with the increasing size, complexity and different styles of designs, it is very much a need.
However, that is supported by actual verification engines and methodologies which are varying considerable with digital, … Read More
A Brief History of Forte Design Systems
When Semiwiki readers see the name Forte Design Systems, they may think of the live bagpipers’ performance that closes the yearly Design Automation Conference. Forte has been the sponsor of this moving end to DAC since 2001. Step with me behind the plaid kilts for a good look at this remarkable company headquartered in San Jose, … Read More
