Digital semiconductor design flows predominantly use library models (typically verilog and liberty formats) for static analyses. Design sizes continue to grow and geometry continues to shrink. Demand for superior performance continue to increase. Accuracy of the library models has become more critical than ever before … Read More
Tag: eda
A Novel Approach to IC Design in the Cloud
Migration to cloud computing for scientific and engineering applications is inevitable. More specifically for IC design, the benefits are significant:
- Common IC design infrastructure to unburden each user from setting up and maintaining a separate infrastructure
- Cloud based IC design enables global collaboration among
Jasper at DAC
Wait, didn’t Cadence just acquire Jasper. Why is there a Jasper at DAC post?
So the big event is lunch on Tuesday, on Treasure Island. For out of towners that is the island in the middle of the bay bridge (actually just half of it). Food trucks, awesome views of the bay, and really cool street performers. There will be street magic,… Read More
Calypto @ #51DAC Must See!
DAC 2014 in San Francisco promises plenty of new information on emerging low power techniques and faster ways to get to working, fully verified RTL using high level synthesis and formal verification. Get the latest from the industry leader in technologies for high level design and verification and low power RTL designby attending… Read More
PrEDAC Mixer
This month’s EDAC mixer is once again at the Savvy Cellar in Mountain View (basicallly in the Caltrain station). It is on May 22nd from 6-8pm.
Get together with your fellow industry peers and insiders at the monthly EDAC Mixer, to the benefit of local charities. You don’t need to donate anything, you just show up and pay… Read More
A Brief History of MunEDA
In 2002, MunEDA was launched under the guidance of EDA academic veterans and IEEE fellows Prof. Kurt Antreich and Prof. Helmut Gräb (TUM Munich Technical University ) which represented 20 plus years of EDA research and experience. All MunEDA tools are combined in a tool suite called WiCkeD[SUP]TM[/SUP]. The tool suite brand was… Read More
Solido Patent Enabling Variation-Aware Custom IC Design
This is patent number twelve for Solido Design Automation THE leading provider of variation analysis and design software for high yield and performance IP and system-on-chip (SOCs). Additional patents are pending on high-sigma analysis, high-dimensional data mining, and other technologies to design and verify custom integrated… Read More
Dassault #51DAC Assault!
This is one of the most aggressive DAC appearances I have seen from Dassault, absolutely. Dassault Systèmes is branded as the: 3D EXPERIENCE Company that provides virtual universes to imagine sustainable innovations. Its world-leading solutions transform the way products are designed, produced, and supported. Dassault … Read More
Aldec is Celebrating 30 Years @ #51DAC!
Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec … Read More
What Do You Do When You Are Not Designing?
DAC is coming up in a month (OMG less than 4 weeks and we are so not ready I hear a hundred marketing people cry out). That gives you four weeks (and a couple of days) to tell Mentor what you do in your spare time that you are passionate about (spare time, I hear a hundred engineers cry out, what is that?) and you could win $300.
For DAC, Mentor… Read More