Fast buses at DAC

Fast buses at DAC
by Paul McLellan on 04-24-2012 at 10:05 pm

UPDATE: there is free WiFi on all buses.

OK, these are not the 128 bit 1GHz buses we have to hear about every day. They go roughly 40 miles in roughly an hour. But they take you from Silicon Valley to DAC and back, and they are cheaper than BART or Caltrain.

For the first time this year, DAC has buses from Silicon Valley to Moscone for DAC. … Read More


I Love DAC

I Love DAC
by Paul McLellan on 04-13-2012 at 1:16 pm

For the fourth year Atrenta, Cadence and Springsoft are jointly sponsoring the “I LOVE DAC” campaign. In case you have been hibernating all winter, DAC is June 3-7th in San Francisco at the Moscone Center.

There are two parts to “I LOVE DAC”. First, if you register by May 15th (and they haven’t all… Read More


#49 Design Automation Conference Deadlines

#49 Design Automation Conference Deadlines
by Paul McLellan on 01-14-2012 at 10:53 pm

Note that there are several DAC deadlines coming up in the next couple of weeks.

The deadline for user track submissions is January 17th (next Tuesday). Submission requires an extended abstract. See here for details.

The deadline for DAC workshops is January 19th (next Thursday). A proposal is required. See here for details.

The… Read More


Solido – Variation Analysis and Design Software for Custom ICs

Solido – Variation Analysis and Design Software for Custom ICs
by Daniel Payne on 08-15-2011 at 7:11 pm

Introduction
When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that’s what I used for my circuit simulations.… Read More


Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm

Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.


Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More


Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)

Synopsys, ARM, Samsung, GLOBALFOUNDRIES (Part 1 of 2)
by Daniel Payne on 06-14-2011 at 12:26 pm

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.

Notes
Why 32/28nm
Lower power, high integration requirements, mobile applications

What is Ready?
IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
Read More


Going to DAC? There’s an app for that

Going to DAC? There’s an app for that
by Paul McLellan on 05-30-2011 at 1:51 pm

Are you going to DAC in San Diego? Do you have an iPhone? In which case Bill Deegan’s dac48 app is something you should install before you get there. It’s free, which makes a nice change from EDA software pricing.

The app substitutes for the various paper, agendas and maps that you need to consult to find exhibitors, check… Read More


Apache at DAC

Apache at DAC
by Paul McLellan on 05-04-2011 at 2:38 pm

DAC is less than a month away, June 6-8th for the tradeshow, longer depending on what other events you might also be attending. Apache is in booth 2448 (marked in red on the DAC floorplan map.

Many of the presentations at the Apache booth will be customers (such as ARM, Xilinx, ST Ericsson, GlobalFoundries and TSMC) discussing various… Read More