On Tuesday Cadence made a big announcement about their new physical implementation offering, Innovus, during the keynote address at the CDNLive event in Silicon Valley. Cadence CEO Lip-Bu Tan alluded to it during his kick off talk, and next up Anirudh Devgan, Senior Vice President, Digital & Signoff Group, filled in more … Read More
Yesterday was the first day of CDNLive. There were three keynotes. The first was by Lip-Bu Tan, Cadence’s CEO (and the Chairman of Walden International that he will be the first to remind you). The most interesting tidbit was that Cadence now has over 1000 people working on IP and that it represents 11% of their revenue. Then… Read More
Apparently that is the case. Honestly my choice would have been Mentor but I can easily make an argument for Cadence based on my discussions with the foundries and their top customers but more on that later.
Fortune Magazine last week added Cadence to the 2015 list of “100 Best Companies to Work For” citing a cultural transformation… Read More
As big of a fan as I am of Social Media there is still nothing like getting up close and personal when collaborating with the fabless semiconductor ecosystem. After 30+ years in Silicon Valley if there is one thing I have learned it’s that “showing up” is the #1 key to success, absolutely.
Speaking of showing up, each year there are three… Read More
High Level Synthesis (HLS) tools have been around for at least two decades now, and you may recall that about one year ago Cadence acquired Forte. The whole promise of HLS is to provide more design and verification productivity by raising the design abstraction from RTL code up to SystemC, C or C++ code. With any acquisition it is natural… Read More
Applications for IoT sensors are becoming more sophisticated, especially for industrial usage. Building optimal sensors for different applications requires multi-domain design, optimization and verification flows. The sensor devices are usually MEMS, and as such have electrical properties that need to be tailored to … Read More
Last weekend I wrote about the Applied Materials earnings call. And over the last couple of years I’ve written about lots of other earnings calls. Most people have never been on an earnings call, I mean in the conference room where the call is being conducted, not just listening. So I thought it might be interesting to describe how … Read More
Introducing on-chip test circuitry has become a necessary criteria for an ASIC’s post manufacture testability. The test circuitry is usually referred as DFT (Design-for-Test) circuit. A typical methodology for introducing DFT circuit in a design is to replace usual flip-flops with special types of flip-flops called ‘scan… Read More
Cadence announced their Q4 and 2014 results yesterday. They are the only one of the big 3 EDA companies whose fiscal year is the calendar year so Synopsys and Mentor will not be joining them in announcing them this week.
I won’t go into the numbers in detail, you can find them all easily enough. But it is a pity that statements like… Read More
In the late 1990s I was the VP Engineering at Ambit Design Systems. We had a synthesis product (called BuildGates, nobody ever forgot the name). Both our own engineers and our customers wanted to be able to take a look at the gate-level netlist that was generated from their RTL. We used a product from a company called Concept Engineering… Read More
