WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®

WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®
by Randy Smith on 09-13-2019 at 10:00 am

I recently wrote about a ClioSoft® study with Google on using cloud platforms for EDA design and the importance of using persistent storage when doing that. ClioSoft will again be sharing important information on design productivity in the upcoming webinar, Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®. … Read More


Low Power Design – Art vs. Science

Low Power Design – Art vs. Science
by Daniel Nenni on 08-21-2019 at 10:00 am

I have heard many times before that low power and mixed-signal design is more Art than Science. I believe this is a misconception. Science is a field that builds upon previous experiences and discoveries. Art primarily seeks out creative differences, things we have not seen before that evoke emotion. The most successful designers… Read More


Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear

Tensilica HiFi DSPs for What I Want to Hear, and What I Don’t Want to Hear
by Randy Smith on 08-16-2019 at 10:00 am

It seems every day we see a new article (or ten) on autonomous driving. It is an especially hot topic, and it will happen someday. For now, we can dream about it, and many people are working on it. But for the present, the technology in a car that commands my attention is audio. I’ve been a musician since 4th grade. I still perform occasionally… Read More


Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!

Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!
by Daniel Nenni on 08-10-2019 at 6:00 am

As more than 343 people (and counting) know, we will be releasing the 2019 updated PDF version of our first book “Fabless: The Transformation of the Semiconductor Industry” via handout at a live webinar. The response has been overwhelming and I want to personally thank you. The webinar will be a brief overview of the book with a question… Read More


Tortuga Webinar: Ensuring System Level Security Through HW/SW Verification

Tortuga Webinar: Ensuring System Level Security Through HW/SW Verification
by Bernard Murphy on 08-08-2019 at 6:00 am

Jason Oberg

We all know (I hope) that security is important so we’re willing to invest time and money in this area but there are a couple of problems. First there’s no point in making your design secure if it’s not competitive and making it competitive is hard enough, so the great majority of resource and investment is going to go into that objective.… Read More


An Important Next Step for Portable Stimulus Adoption

An Important Next Step for Portable Stimulus Adoption
by Daniel Nenni on 07-02-2019 at 5:00 am

Portable stimulus has been a hot topic for a couple of years in the EDA and semiconductor industries. Many observers see this approach as the next major advance in verification beyond the Universal Verification Methodology (UVM), and the next step higher in abstraction for specifying verification intent. The basic idea is to … Read More


The Complexity of Block-Level Placement @ 56thDAC

The Complexity of Block-Level Placement @ 56thDAC
by Tom Dillinger on 06-11-2019 at 10:00 am

The recent Design Automation Conference in Las Vegas was an indication of how the electronics industry is evolving.  In its formative years, DAC was focused on the fundamental algorithms emerging from academic research and industrial R&D, that enabled the continuation of the Moore’s Law complexity curve.  (Indeed, the… Read More


Cadence on 5G Intelligent System Design #56thDAC

Cadence on 5G Intelligent System Design #56thDAC
by Daniel Nenni on 06-10-2019 at 10:00 am

As much as I love all EDA vendors I must say Cadence did the best DAC this year. Great booth, great location, excellent content, and of course a great party. The 5G presentation in the Cadence booth by Ian Dennison was of great interest to me as I am still trying to wrap my head around this whole 5G thing. I was able to meet with Ian privately… Read More


Design IP in 2018: Synopsys and Cadence Increase Market Share…

Design IP in 2018: Synopsys and Cadence Increase Market Share…
by Eric Esteve on 05-07-2019 at 7:00 am

…but ARM, Imagination, MIPS or Ceva have declined and lose market share. Semiconductor design IP market is still doing good in 2018, with 6% growth year over year. It’s half the growth rate seen in 2017, 2016 and 2015 and the growth decline is imputable to bad results from ARM, the market leader, but also from Imagination (#4), MIPS… Read More


EDA Update 2019

EDA Update 2019
by Daniel Nenni on 04-26-2019 at 12:00 pm

Over the last six years EDA has experienced yet another disruption not unlike the Synopsys acquisition of Avant! in 2001 which positioned Synopsys for the EDA lead they still enjoy today. Or the hiring of famed venture capitalist Lip-Bu Tan in 2009 to be the CEO of struggling EDA pioneer Cadence Design Systems. Under Lip-Bu’s… Read More