DATE 2025 Europe: Design, Automation and Test in Europe

DATE 2025 Europe: Design, Automation and Test in Europe
by Admin on 11-12-2024 at 11:30 pm

DATE 2025 offers numerous opportunities to get in contact with the DATE community and to advertise their novel solutions.

Download the DATE 2025 Promotion & Sponsorship Opportunities here

DATE 2025 is the perfect opportunity to present and communicate your technological and business capabilities to scientific, industrial… Read More


Webinar: Spec-Driven Modeling Automation Platform SDEP™

Webinar: Spec-Driven Modeling Automation Platform SDEP™
by Admin on 09-20-2024 at 1:30 pm

SDEP™ provides robust APIs for creating automated reusable modeling flows significantly reducing turnaround time while preserving essential device modeling knowledge.

The platform integrates Primarius‘ latest technologies for data analysis, parameter extraction, and model quality checking. With its flexible GUI and… Read More


Advanced Design & Manufacturing Montréal 2024

Advanced Design & Manufacturing Montréal 2024
by Admin on 06-05-2024 at 2:43 pm

Montréal’s End-to-End Design and Manufacturing Show Returns

Advanced Design & Manufacturing Montréal brings together five advanced manufacturing areas — Design & Manufacturing, Automation Technology Expo, PACK EX, EXPOPLAST, and Powder & Bulk Solids.

This all-in-one, industry-wide event lets you

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Webinar: Automating the Integration Workflow with IP Centric Design

Webinar: Automating the Integration Workflow with IP Centric Design
by Admin on 04-08-2024 at 3:14 pm

(Work email required for verified registration)

During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate … Read More


Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Tessent SSN Enables Significant Test Time Savings for SoC ATPG
by Kalar Rajendiran on 05-08-2023 at 6:00 am

Pattern Generation Block Level ATPG Flow

SoC test challenges arise due to the complexity and diversity of the functional blocks integrated into the chip. As SoCs become more complex, it becomes increasingly difficult to access all of the functional blocks within the chip for testing. SoCs also can contain billions of transistors, making it extremely time-consuming… Read More


Truechip Introduces Automation Products – NoC Verification and NoC Performance

Truechip Introduces Automation Products – NoC Verification and NoC Performance
by Kalar Rajendiran on 11-07-2022 at 10:00 am

Truechip NoC Automation Product

While Truechip has established itself as a global provider of verification IP (VIP) solutions, they are always on the lookout for strategic IP needs from their customer base. Over the last several years, a solid market for Network-on-Chip (NoC) IP has grown, driven by the need to rapidly move data across a chip. Concurrently, the… Read More


Simplifying Requirements Tracing

Simplifying Requirements Tracing
by Bernard Murphy on 06-09-2017 at 7:00 am

Requirements traceability is a necessary part of any top-down system specification and design when safety or criticality expectations depend on tightly-defined requirements for subsystems. Traceability in this context means being able to trace from initial documented requirements down through specification and datasheet… Read More


Can one process handle IIoT safety and security?

Can one process handle IIoT safety and security?
by Don Dingee on 07-20-2016 at 4:00 pm

SemiWiki had another article recently making the case that in IoT applications, safety and security are intertwined, adding that both are important, but they are not the same thing. Mentor Graphics has weighed in with a new white paper trying to tie both issues to a methodology.

Industrial IoT – or IIoT as you’ll often see in shorthand… Read More


Tcl scripts and managing messages in ASIC & FPGA debug

Tcl scripts and managing messages in ASIC & FPGA debug
by Don Dingee on 04-27-2016 at 4:00 pm

Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects… Read More