Upcoming Webinar: Optimized Chip Design with Main Processors and AI Accelerators

Upcoming Webinar: Optimized Chip Design with Main Processors and AI Accelerators
by Kalar Rajendiran on 02-08-2022 at 10:00 am

Expedera DLA IP Benefits

Using the right tool for the job can be extremely important. Well, maybe not in the case of the famed chef Martin Yan who is notorious for using just one knife—a razor sharp wide blade cleaver that doubles as a spatula—for preparing anything and everything he cooks. For the rest of us, though, the right tools can make all the difference.… Read More


#56thDAC SerDes, Analog and RISC-V sessions

#56thDAC SerDes, Analog and RISC-V sessions
by Eric Esteve on 06-14-2019 at 5:00 am

The good news is that the next five DAC events will take place in Moscone Center in San Francisco! If going to Las Vegas from the Bay area is an easy trip, coming from Europe to Las Vegas makes it a 24+hours journey… One obvious consequence was the poor attendance to the exhibition floor. But let’s be positive and notice that the number… Read More


Webinar: How IoT Designs Driven by Cost Power Security

Webinar: How IoT Designs Driven by Cost Power Security
by admin on 02-08-2015 at 8:30 pm

SoCs being developed for the fast growth Internet-of-Things market will sell for and operate on a small fraction of the power of mobile devices’ chips. More importantly, IoT SoCs will be far more vulnerable to hacker attacks than the much better protected chips in portable devices. As a result, designers developing SoCs targeting… Read More


Migrating to Andes from 8051

Migrating to Andes from 8051
by Paul McLellan on 02-11-2014 at 5:21 pm

The 8051 microcontroller has been around for years…decades in fact. It was originally developed in 1980 by Intel. Back then it required 12 clock cycles per instruction but modern cores use just one. While it is still widely used, mostly as an IP core for SoCs, it is running out of steam despite running over 50 times faster than… Read More