Vaysh Kewada is cofounder and CEO at Salience Labs, a company developing an ultra high-speed multi-chip processor that packages a photonics chip together with standard electronics to enable exascale AI. Salience is funded by Oxford Sciences Enterprise, Cambridge Innovation Capital, Arm-backed Deeptech Labs, former Dialog Semiconductor CEO Jalal Bagherli and former Temasek board member Yew Lin Goh. Prior to launching Salience Labs, Vaysh worked at Oxford Sciences Enterprises, a $745M VC fund focused on deep-tech investments. Prior to that, she was a management consultant at McKinsey & Company. Vaysh holds an undergraduate and Masters degree in Physics from Imperial College London, where her thesis focussed on genetic algorithms.
Tell us about Salience Labs?
Salience Labs was spun out of Oxford and Münster universities in 2021 to commercialise an ultra-high-speed multi-chip processor that packages a photonics chip together with standard electronics. By using light to execute operations, we can deliver massively parallel processing performance – bringing ultra-high speed compute to a wide array of new and existing AI processes and applications.
The compute requirements of AI double every 3-4 months, as the world needs ever-faster chips to grow AI capability. The current semiconductor industry can’t keep pace with this demand. What’s required now is not further incremental innovations on transistor technology. If we are to realise the tremendous potential of AI, nothing short of a paradigm shift in the way we compute will do. One that delivers an immediate step change in performance and speed, while also offering a long-term future roadmap of scaling improvements.
Multi-chip processors – ones that package together several platform technologies – is that step-change, allowing us to package electronics together with silicon photonics, and to move compute from electronics to the realm of light. By using light to execute operations, it’s possible to achieve massively parallel performance and deliver high throughput, low latency matrix maths – at the root of almost all AI applications. And it’s possible to do this with clocking speeds in the 10s of GHz – where currently the limitation of even the most cutting-edge chips is just 2-3 GHz.
Why was Salience Labs founded?
Salience was founded with the vision of creating an exa-scale processor, by packaging a photonics chip together with standard electronics. The technology is based on decades of research at University of Oxford and Münster University in Germany.
The key inventors and researchers of the technology: Professor Wolfram Pernice, Professor Harish Bhaskaran and Dr. Johannes Feldmann, are co-founders in the company, giving Salience Labs significant depth of knowledge in this field.
What makes Salience Labs technology unique?
While other photonic chip companies execute operations in the phase of light, we use a proprietary amplitude-based approach to photonics, resulting in modular, dense computing chips clocking at 10’s of GHz. It also allows for high levels of parallelization, by using different wavelengths of light to send many calculations through the chip. Salience uses a multi-chip design, with the photonic processing mapping directly on top of the Static Random Access Memory (SRAM). This novel ‘on-memory compute’ architecture allows for the fast compute in the photonic domain to be fully utilized, delivering an exceedingly dense computing chip without having to scale the photonics chip to large sizes. This architecture can be adapted to the application-specific requirements of different market verticals, making it ideal for realising AI inference use-cases in communications, robotics, vision systems, healthcare and other data workloads.
How has the company evolved since you founded it?
We originally spun-out of the University of Oxford and the University of Münster in 2021 and have just closed our seed round of $11.5 million from a number of leading VCs including Cambridge Innovation Capital, Oxford Science Enterprises and Arm-backed Deeptech Labs participating, plus some leading names in the semiconductor industry including former CEO of Dialog Semiconductor Jalal Bagherli and Yew Lin Goh. Since closing our seed round, our focus has been on the tape out of our next test chip, developing our software models and packaging solutions. We are also building relationships with customers across a range of market verticals.
You are participating in the Silicon Catalyst incubator programme. What has been the impact on the business?
We joined the Silicon Catalyst programme in 2021, right after spinning out from Münster and Oxford Universities. The greatest benefit is the access it gives us to advisors – individuals who have made a significant impact on the global semiconductor industry. In fact, we met our chairman Dan Armburst through the programme, who is a Silicon Catalyst Co-founder and Board Director. Through those advisors, we gained highly valuable commercial introductions to foundries, IP providers, and EDA providers at a very early-stage of the company. It has given Salience Labs’ a commercial jump start. For example, we’ve just closed our seed round but we’re already working with production level foundries on the fabrication of our next test chip. Silicon Catalyst has been a tremendous accelerator for our business.
What can we hope to see from Salience Labs in the future?
We’re at a very interesting point in time where the industry is recognising the potential of multi-chip processors to solve the tremendous processing bottleneck currently hampering AI growth. Salience Labs’ technology has the potential for breakthrough performance and power capability beyond what the established CMOS roadmap offers. We’re talking to customers across a range of market verticals who are excited about the performance improvements silicon photonics will offer and the new AI processes and applications this will enable. We welcome any additional approaches from potential customers who are interested in understanding the capabilities of silicon photonics.
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