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After Five Years, 28nm Future Remains Bright!

After Five Years, 28nm Future Remains Bright!
by Daniel Nenni on 07-09-2015 at 2:00 pm
Categories: Foundries, TSMC

Five years ago TSMC started 28nm mass production and it went on to become one of the most versatile and successful process technologies in history. The first wave was triggered by an unprecedented demand for application processors from smartphone and tablet vendors. Today it’s widely assumed that 28nm demand will continue growing with the introduction of mid- and low-end smartphones, burgeoning Internet of Things applications, and other second-wave opportunities such as automotive.

Not resting on its laurels, TSMC recently announced several significant process improvements to offer its customers and they are increasing capacity to accommodate strong ongoing demand for 28nm solutions.

As we all know, the performance requirement is different for entry level, mainstream, and high-end products. However, today’s performance spec for high-end products will become tomorrow’s mid-range spec so TSMC needs to continue to improve its portfolio by offering a range of options. Accordingly, the company introduced 28HPC to address 64-bit CPU core conversion to roughly 2GHz performance because 64-bit CPU performance is limited by the power budget.

This year they added 28HPC+ that offers 15% faster speed compared to 28HPC. 28HPC+ can allocate more power budget to push CPU/GPC performance significantly over 2 GHz while staying within the same power budget. 28HPC+ also achieves an additional 30% performance at sign-off condition which allows designers to replace the 28HPC LVT transistors with 28HPC+ SVT transistors. As a result, it can reduce leakage by 80% on high-speed sensitive circuits. Equally impressive, TSMC has worked with its design ecosystem partners to support an easy IP migration from 28HPC to 28HPC+. As you can see from the blue box, all that’s needed is to re-characterize the standard cell library and SRAM complier. There is no change of I/Os. And you simply need to re-simulate and fine-tune analog devices in order to enjoy the greater values of 28HPC+.
The next innovation is 28ULP (ultra-low power). It is based on 28HPC with 30% power reduction and optimized for IoT and wearables. It provides a simple power grid, multiple gate length advantages, smaller die size, a broader portfolio of multi-source IPs, and a shorter cycle time that translates to a faster time-to-market. According to TSMC, when compared to FD-SOI, 28ULP is much more competitive in both performance and low-power. 28ULP offers multiple Vt options with multiple gate bias options, versus FD-SOI’s 2 Vt’s with body bias and gate bias at nominal Vdd.

It should be noted that the extensive body bias implementation in 28FD-SOI not only significantly increases design complexity but also die area.

RF is another trend addressed by 28HPC-RF and the proliferation of RF into LTE RF Transceiver and WiFi/BT combo applications. Advanced RF CMOS technology is needed for longer range and higher data rate, especially in mobile communication which is 4G/LTE now. And further demonstrating 28nm adaptability, TSMC is the first foundry to certify these technologies for automotive production. Multiple customers have completed automotive qualifications compliant with AEC-Q100 for grade-one specs.

Given its outstanding track record over the past five years, there is little doubt that the future for TSMC 28nm technology will continue to be very bright and highly productive, absolutely.

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Why Did Intel Pay $15B For Altera?

Why Did Intel Pay $15B For Altera?
by Paul McLellan on 06-30-2015 at 12:00 pm
Categories: Foundries, FPGA, Intel Foundry, TSMC, Xilinx

While I was at the imec Technology Forum someone asked me “Why did Intel pay $15B for Altera?” (the actual reported number is $16.7B).

The received wisdom is that Intel decided that it needs FPGA technology to remain competitive in the datacenter. There is a belief among some people that without FPGA acceleration available for vision processing, search and other algorithms that map better onto a hardware fabric than a processor, then Intel will gradually have more and more competitors in the datacenter. Even if you only put that possibility at 50-50 (say) then the “only the paranoid survive” attitude is to get an FPGA acceleration solution anyway. Of course they don’t need to buy Altera to do that. I’m sure Altera (or Xilinx even) would be happy to sell them all the chips they need. But at some point that technology may need to be embedded in which case having it on the same process already counts for something.

The next question was “Couldn’t they just build an FPGA solution themselves? It wouldn’t cost $15B.” At the technical level I am sure that the answer is that they could do it. Intel has great engineers and if they put their mind to it I’m sure they could produce something.

But I see 3 problems with doing it in-house.

[LIST=1]

  • Time. Intel might be able to design a suitable fabric but how many years would it take them to get it up to a competitive standard. Altera and Xilinx have spent decades doing it. Intel would be trying to catch them from a standing start.
  • Patents. It is basically impossible to design an FPGA without violating Altera and Xilinx’s patents. Those two companies have a cold war of mutually assured destruction. But anyone else would get problems if and when they got commercial traction. Intel would probably get problems even earlier. If (say) Xilinx felt Intel was violating their patents blatantly they may launch. Against an FGPA startup, the most they could win would be their entire cash balance which probably wouldn’t cover the legal fees.
  • Software. FPGA is as much about software as hardware. I once did due-diligence for a VC on a hardware fabric (arrays of tiny CPUs) and told the VC to run away fast because the company didn’t even realize they were basically in a software business, where they had no expertise. They, and Intel, could probably build the hardware fabric. But could they build and mature a software tool chain allowing them to take C and other software languages and move them into the fabric seamlessly? That takes years too.

    Besides, Intel has already tried to grow their own FPGAs from seed with Tabula and Achronix, in both of which they were major investors and provided foundry services. Tabula closed its doors. Achronix’s are still open but rumors are not enthusiastic.

    So if Intel wants a mature FPGA fabric with a working tool chain that allows compilation of offload software into hardware, they pretty much have to buy Altera or Xilinx. I don’t think Lattice have powerful enough software or large enough arrays, it’s not what they do. Xilinx are deep partners with TSMC, 10nm just announced. Altera are partners with…Intel (and TSMC too, to be fair). So easy decision which girl to chase at the dance.

    The next question. “So why would Intel want to run a merchant FPGA business?” I have to say that I agree with the question. If I put myself in Intel’s shoes I wouldn’t want to. Mostly they are shipping TSMC silicon and have no opportunity to move it into an Intel fab. The Intel/Altera 14nm arrays are not even sampling (or even taped out, I hear). For anti-trust reasons they may have had to promise to keep the business going as a condition of the deal closing, but otherwise the first thing I would do is shut it down, or at least not invest in it for the future. It doesn’t need enough wafers to “fill the fab”. And it doesn’t move the needle in revenue either (Altera is a little less than $2B, all TSMC silicon, and Intel is $60B or so). So Altera’s merchant business is a pure distraction from Intel’s business in the datacenter and notebooks.

    Who benefits? Everyone else. The Altera 14nm FPGAs have ARM processors on them. Who in their right mind is going to kick off an ARM-based project on Altera FPGAs now? Xilinx would seem a much safer choice. They are not about to exit the merchant FPGA business, nor switch ARM out for Atom, nor fail to get timely access to ARM’s latest and greatest next-generation cores, or whatever your nightmare of choice is.

    With regards to the acceleration in the datacenter question, there are two outcomes. One, it turns out to be really important, which bodes really well for Intel/Altera but also for the ARM/Xilinx ecosystem, which will be basically everyone else other than Intel, including some powerful players such as Qualcomm. Or, two, it isn’t a major factor. ARM’s partners can still compete on the basis of power, price and physical size and may get some traction. And Intel wasted $15B.

    Also Read: Xilinx in an ARM-fueled post-Altera world

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    TSMC Shows 10nm Wafer!

    TSMC Shows 10nm Wafer!
    by Daniel Nenni on 06-08-2015 at 4:00 pm
    Categories: FinFET, Foundries, TSMC

    If you really want to know why I write about TSMC it is all about ego, my massive ego, absolutely. Blogs about TSMC and the foundries have always driven the most traffic and they most likely always will. Semiconductor IP is second, Semiconductor Design is third, and I don’t think that is going to change anytime soon:

    SemiWiki BI: Daniel Nenni: TSMC: All
    Total Blogs: 137
    Total Views: 878600
    Average: 6413

    SemiWiki BI: Semiconductor IP: All
    Total Blogs: 431
    Total Views: 1641911
    Average: 3810

    SemiWiki BI: Semiconductor Design: All
    Total Blogs: 1367
    Total Views: 4157039
    Average: 3041


    TSMC came to the Design Automation Conference 16 years ago ushering in a new level of collaboration amongst the fabless semiconductor ecosystem. Other foundries have followed and one could argue that they are the center of the DAC universe. In that time TSMC has completed 15 reference flows (the latest being 10nm) with 7,500+ tech files, 200+ PDKS, and more than 8,600 silicon proven IP titles from .35u to 10nm.

    Today, the first day of #52DAC, my prediction of a big crowd has come true. This year the big foundry buzz is around 10nm. TSMC is showing a 10nm wafer for the first time and everybody is wondering if in fact 10nm will arrive in 2016 like promised. I certainly believe it will and so does the majority of the fabless semiconductor ecosystem.

    Let’s take a quick look at the TSMC process node revenue start history just for fun:

    [LIST=1]

  • .35u 1996
  • .25u 1998
  • .18u 2000
  • .13u 2002
  • 90nm 2005
  • 65nm 2007
  • 40nm 2009
  • 28nm 2011
  • 20nm 2014
  • 16nm 2015
  • 10nm 2016
  • 7nm 2017

    Seriously, we are doing four new process nodes in four years? The fabless semiconductor ecosystem is truly an amazing thing. In regards to process ramp challenges, I remember .13u being very difficult because of the new copper interconnect. 40nm was certainly not easy. 40nm was the last node where TSMC gave you the option of using recommended (yield centric) design rules. Which one of these nodes was the most challenging? You tell me. If you have a design horror story please share it in the comments section and I will give you a free Kindle version of “Fabless: The Transformation of the Semiconductor Industry“.

    TSMC has the Open Innovation Platform Theater again this year in booth #1933. You can see the schedule HERE.The other TSMC related #52DAC activities are HERE:

    TSMC’s booth is jam packed, probably because they are giving away iWatches and other cool stuff. TSMC also had some interesting IoT press today, one even mentioning 10nm:

    Imagination and TSMC collaborate on advanced IoT IP platforms
    Imagination Technologies (IMG.L) and TSMC announce a collaboration to develop a series of advanced IP subsystems for the Internet of Things (IoT) to accelerate time to market and simplify the design process for mutual customers. These IP platforms, complemented by highly optimized reference design flows, bring together the breadth of Imagination’s IP with TSMC’s advanced process technologies from 55nm down to 10nm…

    Cadence Announces Collaboration with TSMC on IoT IP Subsystem
    Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) intellectual property (IP) subsystem demonstration platform for TSMC’s ultra-low power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence suite of digital and custom/analog tools, provides the opportunity to simplify IoT designs and accelerate the time to market for mutual customers…

    Synopsys and TSMC Collaborate to Develop Integrated IoT Platform for TSMC 40-nm Ultra-Low-Power Process
    Synopsys, Inc. (Nasdaq:SNPS) today announced a collaboration with TSMC to develop an integrated Internet of Things (IoT) platform on TSMC’s 40-nm ultra-low-power (ULP) process technology. The IoT platform incorporates a broad range of DesignWare® IP, including an integrated sensor and control IP subsystem with the ultra-low-power ARC® EM5D processor core, power-and area-optimized logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an analog-to-digital converter (ADC). The high-performance, low-power IoT platform provides designers with a pre-validated solution that enables them to deliver the energy-efficient, always-on processing required for applications such as sensor fusion and voice recognition…

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    "Cook’s Law" supersedes "Moore’s Law"-its impact on Apple, Samsung, TSMC & Intel

    "Cook’s Law" supersedes "Moore’s Law"-its impact on Apple, Samsung, TSMC & Intel
    by Robert Maire on 05-29-2015 at 7:00 am
    Categories: Foundries, Intel Foundry, Samsung Foundry, TSMC

    Apple drives the semi industry harder than Wintel ever did: Is winning Apple’s chip business a pyrrhic victory? Is 14nm done before it starts? Too short to be profitable?

    Chips marching to an Apple cadence…
    In the “old days” when Wintel ruled the roost and drove the semi industry, it was driving spending cycles based on new versions of Windows that stimulated unit volume of PCs and thus chips.

    New versions of Windows did not specifically demand nor require new technology nodes of Intel processors which were released at the standard “Moore’s Law ” cadence. Windows releases and Intel technology nodes were not interdependent and were relatively loosely linked. It was a “nice to have” if new processors came out at the same time as a new version of Windows but it wasn’t a “must have”

    In today’s world, a new version of the iPhone can’t be released unless a new processor is inside to drive it to new heights. The product, processor and software are inextricably linked.

    Given that Apple is driving the train with its fall, seasonal roll out of the new iPhone every year, everybody else, who supplies Apple (this means semi suppliers) has to be on board or be left behind at the station. In essence this means that Apple is setting the schedule for the next semiconductor technology node roll out, not the semiconductor industry itself or Moore’s Law as it had previously been.

    Apple is forcing and imposing a schedule upon its suppliers, which may be different than a “natural” cadence and likely negatively impacts those who are forced to follow.

    Is 14nm done before it even starts?
    We are amazed by the level of BS in the industry that competing players are throwing around about 14nm and now 10nm. Both Samsung and TSMC are pushing their competing press releases about 10nm in 2016 before the ink is even on the paper for 14nm orders.

    Going by whats in the trade rags and around the industry, we have moved on so quickly from the issues of 14nm and FinFET on to who has the lead at 10nm it makes my head spin. Apple won’t have a product out until the fall and we have already started to talk about who will win the A10 for 2016.

    If we believe the hype (and I’m not sure wether we do or not…) it sounds like 14nm will be another “lite” node much like 22/20nm was. The last “good” node being 28nm. However there are those in the industry that say that 10nm will be another “good” node much like 28nm.

    It feels like 14nm is already “old news” and the PR wars and jockeying for position at 10nm is even more severe than it was at 14nm….and who does this all benefit??….Apple.

    Is Apple chip business a “loss leader”?
    When you take into account the massive effort to ramp, the less than ideal yields and the competitive positioning needed to win Apple’s business its not likely very profitable at the end of the day.

    One of the main reason’s we would suggest this is that the cost of manufacturing semiconductors is primarily the amortization of the manufacturing costs over as many years and products as is possible. If Apple forces chip makers to move on before they get a chance to amortize the cost of equipment and R&D needed to get to that technology node then how do you make money? Certainly not on Apple. The only way you can make money is by trying to amortize that cost on the backs of trailing technology companies and no one wants to pay up for what is perceived as trailing edge devices.

    We think that Apple has made it a more dangerous, potentially much less profitable game by both compressing the technology nodes and forcing them to their own cadence.

    Cook’s Law..
    “Supplier competition goes up exponentially with each new supplier or technology node added”

    The semiconductor industry may be just as much a slave to Apple’s whims as are the Apple slaves at the Foxconn factories in China. Walmart may have a million employees in the US but Apple has more if you count suppliers globally.

    If you are going to be a slave at least be a high priced slave. We have a hard time seeing the semiconductor industry getting better profitability out of Apple given the current competitive supplier dynamics involved.

    We don’t see this changing soon as neither TSMC nor Samsung are likely to drop out of the race. Maybe Apple kicks Samsung to the curb again just to remind them of their place as a supplier but they will keep coming back. Maybe Global Foundries has the right idea as they are currently working on Qualcomm 14nm parts and not Apple A9. Maybe they figured out it was a bad game to play or maybe they were just too late. Apple has been the maestro of playing its suppliers and they continue to write the rules and set the standards

    Can equipment companies win?
    One would think with technology nodes coming fast and furious that equipment companies would be rolling in orders but that is obviously not the case. So where is the disconnect? Business is good but not great on the foundry side of life. Could it be that chip companies recognize that we have “lite” technology nodes, that are relatively short lived and are spending accordingly to not invest too much money in a node thats over as soon as it starts. Could it also be that the equipment for older nodes can get rolled over into new nodes and “reused” more quickly as not as much capacity is needed at trailer nodes as used to be the case in the past?

    Even given these two factors its still going to be hard to not spend incremental money when you start talking about quadruple patterning at 10nm and below. Lots of etch and dep tools, lots of stuff to go wrong needing yield management. EUV is nowhere to be seen at 10nm and 7nm may be “iffy”.

    Likely positive WFE spend trends at 10nm…
    If 10nm turns out to be more than the “lite” 22/20nm node or what seems like a “lite” 14nm node that would obviously be good for the likes of Lam, AMAT & KLAC. Less so for ASML.

    As far as the stocks go, we remain positive on Lam and KLAC, feel that AMAT is fully valued and ASML is overvalued…..based on these longer term trends. These should be interesting topics at the upcoming SemiCon West show……

    Robert Maire
    Semiconductor Advisors LLC


    Also Read:     Why does Apple do business with Samsung?

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    Why does Apple do business with Samsung?

    Why does Apple do business with Samsung?
    by Daniel Nenni on 05-26-2015 at 10:00 pm
    Categories: Foundries, Intel Foundry, Mobile, Samsung Foundry, TSMC

    The Apple and Samsung relationship is an interesting one. On one hand they have co-developed some of the most innovative products on the market today (iPod, iPhone, iPad, iWatch) yet they are fierce competitors in the mobile market. Some call this type of business relationship “frenemies” others refer to the old Italian proverb “keep your friends close, but your enemies closer.” Personally I refer to it as “foundry business as usual.” Let’s take another look at the Apple/Samsung relationship and see if we can get a better picture of what is really going on here. This of course is based on my experience, observations, and opinions so feel free to correct me if I’m wrong, but I’m not.

    Apple became a chip company in the early 1990s with the assistance of VLSI Technology. This was using the ASIC business model where Apple could “toss” an RTL level design over to VLSI and have them deliver finished chips. The first chip was for Apple’s PDA, the Newton, which lost out to the much easier to use BlackBerry and Palm Pilot.

    The smartphone (iPhone) was the next device to usher in semiconductor design at Apple. In 2007 the first iPhone was powered by the APL0098 SoC designed by Apple and the newly created Samsung Foundry Division using the same ASIC business model that VLSI Technology pioneered. The first chip used Samsung’s 90nm technology which was one process behind TSMC’s 65nm that offered twice the gate density and a power reduction of up to 50 percent.

    The next two iterations of the Apple SoC were released in 2008 and 2009 using Samsung’s 65nm technology. At the same time TSMC was delivering 40nm chips with twice the density of 65nm with significantly reduced power requirements. In 2009, 2010, and 2011 Apple used Samsung’s 45nm which delivered density and power requirements just below TSMC’s 40nm. In 2012 and 2013 Apple used Samsung’s 32nm process but TSMC was already at 28nm which again offered increased density and lower power. At the end of 2013 (iPhone 5+ and iPad Air) Apple used Samsung’s 28nm. Apple also ushered in the 64-bit smartphone with the iPhone 5s beating industry SoC leader Qualcomm.

    For the iPhone6 and iPad Air2 in 2014, Apple switched to TSMC’s 20nm which offered a 1.9x density and 25% power advantage over 28nm. The switch from Samsung Foundry to TSMC is a hotly debated topic especially since Apple is now back at Samsung for the 14nm A9 to be released in September of 2015. According to analyst estimates, Apple paid Samsung $2.7 billion for chips in 2014 which is significantly lower than the $4.3 billion Apple paid Samsung in 2013. So yes, the Apple business is a very big deal for the foundries, absolutely.

    Apple claimed its semiconductor manufacturing independence with the 2008 acquisition of P.A. Semiconductor and the 2010 acquisition of Intrinsity which enabled them to move from the ASIC business model to the fabless semiconductor powerhouse they are today. If you want my opinion, which clearly you do if you are reading this, Apple bases the process technology decisions on technology and the ability to deliver said technology, simple as that.

    I know that Apple evaluated TSMC’s 28nm for the A6 and A6x SoCs but since TSMC was the only foundry yielding at the time TSMC’s 28nm pricing and capacity were in question. At 20nm however, Apple wrote TSMC a very large check to get right-of-first-refusal and most-favored-nation pricing which squeezed out competing SoC vendors (QCOM, MEDIATEK).

    At 14nm Samsung developed an LP process specifically for Apple which started risk production in Q4 of 2014 making it viable for the Apple A9 SoC (iPhone 6+) release in Q3 2015. The big shocker here is that Samsung released their own 14nm SoC (Exynos) for their flagship mobile device the Galaxy S6 in the first half of 2015 beating everyone’s 14nm delivery expectations, including my own.

    TSMC was two quarters behind Samsung with their higher performance 16nm FinFET++ implementation which will be used in the lower volume Apple A9x SoC business for the iPad refresh in Q4 2015 (the A9 versus A9x volumes are reportedly 70% versus 30%). I also heard that Apple evaluated Intel Custom Foundry 14nm, but to no avail.

    10nm will be the next foundry battleground. Samsung and TSMC have both discussed taping out 10nm customer designs in the fourth quarter of 2015 which fits the timeline for Apple’s next product refresh using the A10 and A10x SoCs. Intel on the other hand has been very quiet which is not necessarily a good sign for the competition. Intel surprised the industry with 22nm FinFETs. Another 10nm surprise could certainly be in the making. My guess is that Apple will go to TSMC for 10nm but at this point it is just a guess.

    Bottom line: Today, Apple is clearly the most influential foundry customer worth billions of dollars in revenue annually. Apple’s regular product refresh is now driving the foundries harder than I have ever seen and that includes Intel and Samsung. Competition is what makes the fabless semiconductor ecosystem strong and who better than Apple to lead that effort?

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    TSMC 10nm Readiness and 3DIC

    TSMC 10nm Readiness and 3DIC
    by Paul McLellan on 05-03-2015 at 1:00 am
    Categories: EDA, FinFET, Foundries, IP, TSMC

    At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

    Around the turn of the millennium Suk actually worked for me. In fact, he took over my job running marketing for IC, which is what Cadence called all of the back end tools for both analog and digital. After that he went to Magma (which of course was acquired by Synopsys). At the start of his career he had also, like me, worked for an ASIC semiconductor company, VLSI Technology in my case and LSI Logic for Suk, so we both have what I like to call “silicon in our veins”. That was followed by his first stint at Cadence before going back to semiconductor at Texas Instruments. He joined TSMC six years ago where he is now senior director of design infrastructure marketing, based in Taiwan.

    First there are the new 28nm processes, 28HPC+ and 28ULP. 28HPC+ is for high performance, a speed gain of about 15% for the same leakage, or a reduction of 30-50% in leakage for the same speed. There are also new standard cell libraries for this process with 9 and 7 track libraries (compared to 12T/9T before). The 28ULP (for ultra-low power) process is for IoT applications with a lower operating voltage of 0.7V (versus 0.9V for 28HPC+). This new process joins the other two ULP processes 55ULP and 40ULP. There is also a library benchmarking kit to help design groups find the best combination of libraries to meet their target PPA.

    The design flows are largely in place for both processes. The foundation IP is ready for 28HPC+ with other IP becoming available from now through Q1 of next year. A lot of the IP for 28ULP is still in the planning phase.

    Next Suk talked about the 16FF+. The design flows and IP portfolio are all in place with almost everything characterized in silicon. At the event a new 16nm process 16FFC was announced. This is intended for cost-sensitive consumer applications. The foundation IP should be available in Q4 of this year, with interface IP coming in Q2 of 2016.

    There was a lot of detailed information about 10nm which TSMC were talking about for the first time.

    EDA tool support is as follows:

    • Automatic Place & Route: Synopsys, Cadence, Mentor
    • DRC: Synopsys, Cadence, Mentor
    • LVS: Synopsys, Cadence, Mentor
    • RCX: Synopsys, Cadence, Mentor
    • STA: Synopsys, Cadence
    • EM/IR: Synopsys, Cadence, Ansys
    • SPICE: Synopsys, Cadence, Mentor
    • FastSpice: Synopsys, Cadence, Mentor
    • Custom Design: Synopsys, Cadence

    The IP library for 10FF is targeted at several different application areas: smartphone, tablet/ultrabook, networking, CPU/GPU/FPGA. The various IP very in their state of readiness from being full characterized from silicon test chips, or waiting for silicon characterization (but able to be used in design starts), to blocks that are still in development. In detail, IP for 10FF is available as follows:

    • Standard cell: silicon report
    • GPIO/ESD: silicon report
    • PLL: pre-silicon design kit
    • SRAM compiler: silicon report
    • ROM compiler: in development
    • Electrical fuse: silicon report
    • OTP: in development
    • DDR4: pre-silicon design kit
    • LPDDR4: pre-silicon design kit
    • PCIe: pre-silicon design kit G3 & G4
    • MIPI: pre-silicon design kit G2 & G3
    • SATA II/III: in development
    • 10G serdes: in development
    • USB 2/3: pre-silicon design kit
    • HDMI/MHL/DP: in development

    The 3DIC technologies offer offer heterogeneous die stacking and packaging solutions for high speed, high density and low cost applications. There is thru-silicon-via (TSV) implementation with accurate modeling, an integrated 3D testing methodology, wide-IO interface signal integrity and chip-package-system thermal analysis. The design flow is completely ready, with design kits ready.


    TSMC has the broadest IP portfolio in the industry with IP from 0.35um down to 10nm with nearly 9000 different IP titles.

    The China Symposium is next week in Shanghai on 5/7 (in Chinese). European symposia are in Amsterdam on 6/16 and Herzliya on 6/29. The TSMC symposium page is here. There will be one in Yokohama but the date is not yet decided. But save the date 9/19 for the OIP Ecosystem Forum in Santa Clara. Details are here.

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    Motley Fooled by FinFETs!

    Motley Fooled by FinFETs!
    by Daniel Nenni on 04-28-2015 at 10:00 pm
    Categories: FinFET, Foundries, Intel Foundry, TSMC

    There was an article on Motley Fool recently detailing Intel’s 14nm FinFETs and comparing them to TSMC. Unfortunately the author has zero semiconductor education or experience even though he writes with authority on all things semiconductor. He also has no shame in using outdated papers from conferences he did not even attend to make his misguided point. The things people do for a penny per click… and yes I did speak to him privately about this but he stands by his article and left it to me to prove him wrong, which is why I write this now.

    Intel Corporation to Detail 14-Nanometer System-on-Chip Technology at VLSI Symposium

    According to SemiWiki experts, Motley Fool’s article misrepresents some of the intricacies associated with FinFets and how drive currents are defined. On the face of it, Intel’s 14nm announcement looks impressive; 37-50% drive current improvements over 22nm, who could complain about that? Unfortunately a slightly deeper dive reveals some issues with this conclusion. Intel, at various meetings, including their analyst meeting back in November 2014, proudly announced their fin pitch scaled from 60nm to 42nm, while their fin height increased from 34nm to 42nm. All good assuming I have similar current/micron of fin perimeter (also called Weff which for one fin is 2* height + top width, but more on that later). With more fins/micron and taller fins, I should be able to have much better performance.

    However, if you read their IEDM 2014 paper carefully, you will notice that all Intel’s drive current numbers are quoted per micron of drawn width, i.e. for one micron of top view silicon width. Now taking the assumption above of same current/micron of fin perimeter, how much performance improvement should I get per drawn micron? Using Intel’s own numbers, we have 60/42 =1.43X more fins/micron and fins are 42/34 = 1.24X taller, so all in all we should get 1.76X more drive current/drawn micron. In others words, at equal drive current per micron of fin perimeter, we should have seen 76% more current from these tighter taller fins, but Intel is reporting only 37-50%. Clearly the drive current per effective micron is going down. Intel struggled with their 14nm yield, this suggests they may have also struggled with their device performance.

    The article goes on to compare Intel to TSMC 16nm FinFet however the author does not realize that the TSMC 2013 IEDM paper was quoting drive currents/Weff as described above, not per drawn micron. TSMC actually pointed this out in their 2014 IEDM presentation. TSMC also showed even better performance in their 2014 paper than the earlier 2013 version, hence the new process name 16FF+. So in the end, how do they stack up? If you use the Intel’s per drawn micron metric, TSMC 16FF+ has ~10% more drive current than Intel 14nm (all other things being equal including leakage and voltage). If you use another metric like current/fin, or current/Weff, TSMC has an even stronger advantage.

    That is why during the TSMC symposium last month Dr. BJ Woo emphatically stated TSMC had “the best” transistor in the 14-16nm technologies. It will be interesting to watch how this unfolds as 10nm process details are disclosed. In my 30 years in the semiconductor industry I don’t remember a more exciting time, absolutely.

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    TSMC Unleashes Aggressive 28nm Strategy!

    TSMC Unleashes Aggressive 28nm Strategy!
    by Daniel Nenni on 04-11-2015 at 10:00 pm
    Categories: Foundries, TSMC

    The most interesting presentation at the jam-packed TSMC Symposium last week for me was “Advanced Technology Updates” by Dr. BJ Woo. Coincidentally, I met with BJ during my last visit to Fab 12. Much of what we discussed was about TSMC being more aggressive this year but I wasn’t able to really connect the dots until her presentation. The example I will use here is 28nm but it certainly applies to all of the TSMC process nodes moving forward.

    First let me tell you that BJ is engaging and a very credible semiconductor executive. She spent the majority of her 30 year career at Intel in Santa Clara designing both DRAM and microprocessors (she has 13 patents). In 2009 BJ joined TSMC taking responsibility for the advanced technology roadmap at 28nm and 20nm and today is Vice President of Business Development.

    According to recent press releases and the resulting comments by analysts, who don’t know any better, other foundries are eating away at TSMC’s 28nm stronghold. Articles like that will get you lots of clicks but they are misleading. Remember, there are two versions of 28nm: gate-first and gate-last HKMG. Moving a TSMC gate-last 28nm design that is in production with 90%+ yield to a new gate-first process is absolute madness. Even moving a production design to a new gate-last process that is supposedly “T” compatible (UMC and SMIC) is risky. But of course it will happen because if you are negotiating a better price from one vendor you have to actually be in the position to use another vendor to even be at the negotiation table.

    Having the best yielding process does not just give you the lowest cost, it also gives you better design margins and that is the point TSMC made at the symposium. Today TSMC has five versions of 28nm: HP (high performance), HPM (high performance mobile), HPC (high performance computing), HPL (high performance low power), and LP (low power). Two additional processes were added: HPC+ which is an even faster version of HP and ULP which is ultra-low power for IoT and other battery powered applications.

    28HPC+ is more compact with 9 and 7 track cell libraries versus 12 and 9 track for 28HPC. The design rules are the same but it has better design margins which offers 15% more performance. 28ULP looks a lot like 55ULP and 40ULP that are already in production. Compared to the associated LP processes, ULP processes can further reduce operating voltages by 20% to 30% to lower both active power and standby power consumption resulting in a 2x-10x increased battery life. IoT and wearable devices are the target applications for ULP processes of course.

    The other big 28nm announcement that BJ made is that the TSMC 28nm is now qualified for automotive work which is an industry first. Given the growth of electronics in our cars and the coming autonomous vehicles this is a very big deal for sure.

    In the same vein, BJ also talked about a new 16nm process coming called 16FFC, the C meaning compact. It is a more economical version of 16FF+ aimed at cost and power sensitive markets. Power is said to decrease by more than 50% and the pricing will be very competitive for mainstream markets.

    Again, when I met with BJ she said TSMC would be very aggressive moving forward and she had a definite twinkle in her eye and now I know why. What a great year for the fabless semiconductor ecosystem, absolutely!

    Also read: TSMC Processes Galore

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    ANSYS Enters the League of 10nm Designs with TSMC

    ANSYS Enters the League of 10nm Designs with TSMC
    by Pawan Fangaria on 04-09-2015 at 7:00 pm
    Categories: Ansys, Inc., EDA, Foundries, TSMC

    The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award. Read “ANSYS Tools Shine at FinFET Nodes!”. Just before this Intel also certified ANSYS tools at 14nm Tri-gate process as written in another article, “Intel & ANSYS Enable 14nm Chip Production”. And this week, TSMC has certified ANSYS Power Integrity and Electromigration (EM) solutions for 10nm FinFET process node. It’s amazing progress! Read the press release here.

    ANSYS portfolio of products was showcased in the TSMC Technology Symposium held in San Jose, California on 7[SUP]th[/SUP] April, 2015. ANSYS’ RedHawk and Totem were certified by TSMC for 10nm FinFET DRM and Spice models. These tools were certified to provide solutions for static and dynamic voltage drop analysis and advanced signal and power EM verification that are required for ultra-low power and high performance SoC designs at 10nm for mobile, computing and networking applications.

    At 10nm process node the devices are left with extremely low noise and reliability margins and FinFET’s structure is typically prone to increasing self-heat.

    As shown in the picture, heating happens at the device (FEOL) as well as interconnect (BEOL) levels and hence both need to be considered. At sub-28nm process nodes, as we go down the node, the current density increases and makes the device increasingly vulnerable to EM. In a FinFET the current density can be generally 25% more than that in a planar transistor. Also the narrow 3D fin structure and the lower thermal conductivity of the SiO2 dominated substrate can cause local heat to get trapped.

    With such tough challenges and extremely tight window of accuracy, it’s critical to ensure power integrity across the chip, package and board. And an accurate EM analysis at all levels is a must. There are some key critical enhancements added into ANSYS tools to provide the kind of accuracy and versatility needed for the EM, power integrity and reliability solution at 10nm.

    To support multi-patterning technology, ANSYS solution provides color-aware resistance extraction and EM analysis capability. And there is a complete system-to-block level EM analysis flow with color-aware metal-fill capability that delivers higher yield and performance along with accurate EM analysis.

    To address the increasing difference in the current between signal and power rails, ANSYS solution provides various approaches to apply appropriate EM rating factors for signal and power analysis. At 10nm, there can be measurement issue between the drawn trapezoidal shape and the physical implementation of a wire in silicon. ANSYS provides a comprehensive wire width adjustment solution to compensate for the difference that leads to more accurate results in the EM analysis.

    ANSYS solution provides thermal-aware EM methodology. Above diagram shows the Thermal-aware EM Flow at TSMC for the 16nm FF+ process node that uses RedHawk, Totem and Sentinel-TI. RedHawk/Totem along with Sentinel-TI uses foundry data to accurately compute the self-heat temperature on an IP or SoC. The temperature can be analyzed at instance or metal layer basis. A Chip Thermal Model (CTM) is generated for back-annotation into RedHawk or Totem. This methodology helps avoiding over-heating of the device, thus increasing its lifetime and reliability.

    With increasing complexity and sizes of SoCs at lower nodes, challenge of managing capacity, performance, and parasitic effects also increases. RedHawk/Totem uses a novel Distributed Machine Processing (DMP) capability that can handle large power delivery network (PDN) and perform flat simulation with high performance and small memory footprint. RedHawk-CPA provides chip-package co-simulation and co-analysis within a unified environment that ensures integrity of power delivery on the complete chip and takes into account the impact of package parasitic, thus avoiding undesired hotspots.

    The overall comprehensive solution provided by ANSYS delivers highly accurate results as needed at 10nm FinFET node and also reduces design turnaround time through its innovative methodology, algorithms, and multi-physics simulations. The Power Integrity and EM solutions are ready for 10nm FinFET based early design start. On earlier technologies, ANSYS solution for SoC/IP power integrity, noise, and reliability sign-off has been proven on thousands of successful silicon wins.