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WP_Term Object
    [term_id] => 158
    [name] => Foundries
    [slug] => semiconductor-manufacturers
    [term_group] => 0
    [term_taxonomy_id] => 158
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1243
    [filter] => raw
    [cat_ID] => 158
    [category_count] => 1243
    [category_description] => 
    [cat_name] => Foundries
    [category_nicename] => semiconductor-manufacturers
    [category_parent] => 0

Moore’s law limitations and gravitational collapse at lower process nodes

Moore’s law limitations and gravitational collapse at lower process nodes
by Vaibbhav Taraate on 10-05-2015 at 4:00 pm

 As stated in my previous article, about the complexity of the SOC with billions of transistors. It is essential to consider the real practical scenario for the two dimensional verses three dimensional structure of the chip. Although the new technological changes and evolution for the shrinking process node can create ease for the design of SOC still there is limitation due to fundamental laws.

At the lower process node there is limit due to Einstein’s relativity theory. As none of the particle can travel through the material with more than speed of light ( Mainly affected due to dielectric constants). So the reality is the uneven distribution of power density at Tera Hertz of frequency. Even if the three dimensional routing architecture is also used then it will give birth to the variation of electric field across the surface of interconnect and it creates issues for the interconnect modeling and interconnect test validation. So this area need to be evolved. The 2 dimensional architecture of any chip can have variation in the form of ( x,y,p,v,t) but for the three dimensional chip architecture has always variation in the form of (x,y,z,p,v,t,E and power density) so it really involves the eight dimensional analysis below 14nm process node.

According to uncertainty principle published during 1925-1927 by Heisenberge ” The more precisely the position is determined, the less precisely the momentum is known in this instant, and vice versa.” So for the 3 dimensional chip architecture it involves the tight relationship between the energy , time and even space and time. Due to shrinkage as atomic spacing reduces it creates the vertical and horizontal components at the surface of conductor and it leads to the power losses across the surface and can affect on the overall data convergence. For billion transistor SOC at Giga Hertz or Tera Hertz the performance is real bottleneck due to the atomic spacing and the speed of data transfer between the carriers.

According to Landauer’s principle” There is minimum possible amount of energy required to erase one-bit of information and called as Landauer’s limit.” So according to Landauer’s principle if observer looses the information then it loses the ability to extract work. So for SOC at the lower process nodes it has greater impact in the data transfer from one node to the billion of nodes.

According to Bekenstein the black holes should have well defined entropy. And even if we consider the variation of the temperature across the chip then according to the Bekenstein bound, ” There is maximum amount of information can be stored in the space which has finite energy” By considering this for the 3-dimensional SOCs the real issue is the decay of the data transfer at the higher speed due to the losses across the surface of interconnect and even it can lead to the gravitational collapse due to uneven distribution of the power density at lower process node at higher speed .

So below 14 nano-meter for billion density SOC the performance and life of SOC is the real challenge for any chip designer and due to that shrinkage will have limitation even with the three dimensional architecture of the chip. The effect of the data transfer from one of the node to billions of nodes and gravitational collapse can be much higher below 10 nano-meter process node.

In such scenario the doubling of transistor in Integrated Circuit will affect heavily and it will take much more time to double the transistors. So according to my mathematical calculations and analysis using the fundamental laws, “For billion transistor SOC below 10 nano-meter will take 36 to 38 months to double the transistors with the required improved performance.”.

So at the lower process node there is requirement of the real evolution of the manufacturing processes and even design flows. So the universal modification in the Moore’s law is very much required. And the modified Moore’s law can be stated as ” The number of transistors in dense Integrated Circuit has to be doubled in approximately 36 to 38 months”. Even this will have greater impact on Rock’s law and manufacturing processes for three dimensional integrated circuits!

Also read: Moore’s law observations and the analysis for year 2019

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