Ion Implant – Its Not Just for Doping Anymore

At the heart of fabricating integrated circuits is the ability to selectively change the electrical properties of the semiconductor substrate. This key to fabrication is accomplished by doping – introducing atoms locally into the semiconductor substrate.

In the early days of the semiconductor industry doping was accomplished by creating a pattern on the surface of the semiconductor substrate typically in an oxide film and then depositing a doped glass over the surface. A subsequent heat treatment would then diffuse the dopants from the glass into the exposed semiconductor surface in some areas and the dopants would be blocked by the glass in other areas.

With the introduction of ion implantation for doping, solid source doping has largely disappeared (although Intel recently brought it back for one application in their 14nm process). Ion implantation utilizes a particle accelerator to inject dopants into the semiconductor material with high energies. Ion implant has several advantages over solid source doping, first and foremost is better control of the amount of dopant introduced. Ion implant can also better control the depth of the dopants and utilize photoresist as the mask for doping as opposed to requiring a film that can withstand high temperature; and Ion implantation can introduce nearly any atom of interest and does it at low temperature.

Recently the semiconductor industry has begun the evolution of logic processes from planar devices to fully depleted devices such as FinFETs and FDSOI. This transition greatly improves the electrostatic control of the gate over the channel of the device and dramatically reduces leakage. This transition also reduces the need for ion implantation. As semiconductor devices have shrunk into the deep sub-micron range the control of threshold voltages has driven a significant increase in the need for ion implantation. Different threshold voltages have required threshold adjust implants for NMOS and PMOS for each threshold voltage. At deep sub-micron dimensions the halo implant at the drain extension step and even the source/drain contact implants also have to be tailored for each threshold voltage. An additional threshold voltage can require as many as 13 implants at 40nm and smaller nodes! With FinFETs threshold adjust implants are still used but there are no halo implants so only extensions implants for NMOS and PMOS are required and raised source/drains are used with no implants. FDSOI further reduces the implants required by controlling threshold voltages with biasing instead of implants. At first glance this all seems like bad news for implant companies.

At SEMICON West in 2014 I attended an Axcelis presentation on the use of implants to change the material properties of wafers. Current state-of-the-art implanters can vary the dose implanted into a wafer radially. So if for example you had a CMP process that removed material faster at the edge of a wafer versus the middle of the wafer you could implant a higher dose of an implant specie in the center of the wafer than the wafer edge increasing the CMP removal rate in the center and creating a CMP/Implant process combination that is uniform across the wafer. This new application for ion implant was presented as having the potential to maintain or grow the market for implanters even though doping applications were declining. Some applications for this technique:

1. Amorphization
2. Modifying CMP removal rates
3. Modifying Etch rates
4. Hardening photoresist
5. Reducing photoresist pattern line-edge-roughness (LER)

At the time I thought this was an interesting potential application but I wasn’t aware of it actually seeing much use. I will comment that I could see a lot of potential for it, implant steps are relatively inexpensive particularly if no photoresist mask is required at only $1 to $2 per implant for a 300mm wafer.

Since then I have become aware that this technique is rapidly being adopted with some logic processes using materials modifications implants 10 or more times per wafer. On the memory side the usage is lower, more in the 2 to 5 implants per wafer but it is growing as well. As process linewidths continue to shrink this is a technique that will likely see increased adoption. In most cases the specie being implanted is similar to the material it is being implanted into so these implants don’t show up on reverse engineering analysis of parts but they are being used today!