Breaking the Thermal Wall: TSMC Demonstrates Direct-to-Silicon Liquid Cooling on CoWoS®

 In a landmark presentation at the 2025 IEEE Electronic Components and Technology Conference (ECTC), TSMC unveiled a groundbreaking advancement in thermal management: Direct-to-Silicon Liquid Cooling integrated directly onto its CoWoS® platform. This innovation, detailed in the paper “Direct-to-Silicon Liquid Cooling Integrated on CoWoS® Platform,” addresses the escalating thermal challenges posed by HPC and AI applications, where power densities are surging beyond traditional cooling limits. As AI accelerators and data center chips push thermal design power toward kilowatt levels, TSMC’s solution promises to shatter the “thermal wall,” enabling denser, faster, and more efficient semiconductor designs.

The “thermal wall” refers to the fundamental barrier where heat generation outpaces dissipation capabilities, throttling performance and reliability in advanced nodes. With the rise of 2.5D/3D packaging technologies, chips now integrate multiple dies, high-bandwidth memory (HBM) stacks, and interposers on a single package, amplifying power densities to over 4.8 W/mm². Air cooling, once sufficient for consumer-grade processors, falls short for HPC workloads. Even advanced air-cooled heatsinks struggle with TDPs exceeding 1 kW, leading to hotspots that degrade silicon integrity and limit clock speeds. Liquid cooling has emerged as a necessity, but conventional methods—relying on bulky external loops or thermal interface materials (TIMs)—introduce inefficiencies, adding thermal resistance and manufacturing complexity.

TSMC’s Direct-to-Silicon Liquid Cooling redefines this paradigm by embedding microfluidic channels directly into the silicon structure, bypassing TIMs for near-zero thermal impedance. At the heart of this technology is the Si-Integrated Micro Cooler, a silicon-based solution fusion-bonded to the chip’s backside. Demonstrated on a 3.3X-reticle CoWoS®-R package—a massive ~3,300 mm² interposer supporting multiple logic dies and HBM stacks—the system achieves junction-to-ambient thermal resistance (θJA) as low as 0.055 °C/W at a coolant flow rate of 40 ml/s. This outperforms lidded liquid cooling with TIMs (0.064 °C/W) by nearly 15%, enabling sustained operation at over 2.6 kW TDP with a temperature delta under 63°C.

CoWoS®  is TSMC’s flagship 2.5D packaging technology, pivotal for AI giants like NVIDIA’s GPUs and AMD’s Instinct accelerators. It stacks chips on a silicon interposer for ultra-high interconnect density, supporting up to 12 HBM4 stacks in future “Super Carrier” iterations spanning 9 reticles. However, as interposers scale to 2,500 mm² or larger, heat flux intensifies, risking electromigration and yield loss. The IMC-Si integrates seamlessly into CoWoS®-R and upcoming CoWoS®-L variants, which incorporate backside power delivery networks (BSPDN) and embedded deep trench capacitors (eDTCs) for enhanced power stability. Microchannel designs—featuring square pillars, trenches, or flat planes—optimize fluid dynamics, with pillar structures proving superior for turbulent flow and heat extraction.

The demonstration highlights practical viability. TSMC tested prototypes with deionized water as coolant, achieving power densities exceeding 7 W/mm² on logic chip backsides. Fusion bonding ensures hermetic seals, preventing leaks in high-pressure environments, while low-temperature processes maintain compatibility with 1.6nm-class nodes. Early results show no degradation in electrical performance, with signal integrity preserved across hybrid bonding interfaces.

This breakthrough extends beyond cooling; it’s a cornerstone of TSMC’s 3DFabric ecosystem, aligning with “More than Moore” strategies like hybrid bonding and CMOS 2.0. By eliminating TIMs, it reduces assembly costs and variability, while enabling trillion-transistor monolithic-like systems. For data centers, it slashes rack-level power—potentially halving cooling infrastructure needs—and supports immersion-compatible designs. In edge AI and 5G, compact IMC-Si modules could fit mobile HPC, boosting efficiency in autonomous vehicles and AR/VR.

Challenges remain: scaling microfluidic fabrication to high volumes, ensuring coolant purity to avoid corrosion, and integrating with emerging materials like silicon carbide interposers for even higher thermal conductivity. Yet, TSMC’s track record—powering 80% of advanced AI chips—positions it to lead commercialization by 2027.

Dr. Kevin Zhang, TSMC’s Deputy Co-COO and Senior Vice President, emphasized: “Direct-to-Silicon Liquid Cooling breaks the thermal wall, unlocking the full potential of CoWoS® for exascale AI. This isn’t just incremental; it’s transformative for sustainable computing.”

As AI workloads explode, TSMC’s innovation heralds a cooler, greener future for semiconductors, where heat is no longer the limiter but a solved equation.

Also Read:

Teradyne and TSMC: Pioneering the Future of Semiconductor Testing Through the 2025 OIP Partner of the Year Award

Sofics’ ESD Innovations Power AI and Radiation-Hardened Breakthroughs on TSMC Platforms

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025