Through my contacts at SemiWiki I was introduced to a mixed signal IP company named SilabTech, and then decided to interview the founder and CEO, Sujoy Chakravarty.
Sujoy Chakravarty, CEO and Founder
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AMS IC Design at SilabTech
How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB LiveAllegro MicroSystems’ experience with yieldHUB Live shows how…Read More
Interview with Sweta Gupta, VP of Engineering of Analog BitsSweta Gupta is the Vice President of Engineering…Read More
WEBINAR: Porting, Analysing & Optimising AI Models onto Edge GPUsModern AI models are opening up new possibilities…Read More
Using AI for Root Cause Analysis of Simulation FailuresI’ve been working with AMIQ EDA for almost…Read More
Agentic AI accelerates 3D IC engineering for the AI factory eraBy Sudarshan Deo, software R&D Manager for 3D…Read More
Schematic Capture and SPICE in the Cloud
A SemiWiki member mentioned CircuitLaba few months back so I took a look at it today and share my first impressions.… Read More
Power and Reliability Sign-off – A must, but how?
At the onset of SoCs with multiple functionalities being packed together at the helm of technologies to improve upon performance and area; power, which was earlier neglected, has become critical and needs special attention in designing SoCs. And there comes reliability considerations as well due to multiple electrical and … Read More
Premier Gathering for Semiconductor Professionals!
The US Executive Forum hosted by the Global Semiconductor Alliance is coming up on September 25th at the beautiful Rosewood Sand Hill Hotel in Menlo Park. Over 150 executives from the semiconductor and technology industry will attend creating a truly unique opportunity to listen to some of the world’s foremost speakers… Read More
Lynn Conway’s Story
If you are my age, you know that the most influential book in that era on VLSI design was Carver Mead and Lynn Conway’s textbook, blah VLSI blah. Nobody can remember exactly what its title was, it was just referred to as Mead and Conway. In my opinion it was the most influential book on semiconductor design ever. It opened up VLSI… Read More
What Applications Implement Best with High Level Synthesis?
RTL coding using languages like Verilog and VHDL have been around since the 1980’s and for almost as long a time we’ve been hearing about High Level Synthesis, or HLS that allows an SoC designer to code above the RTL level where you code at the algorithm level. The most popular HLS languages today are C, C++ and SystemC.… Read More
Epitaxy: Not Just For PMOS Anymore
At Semicon I met with Applied Materials to learn about epitaxy. This is when a monocrystalline film is grown on the substrate which takes on a lattice structure that matches the substrate. It forms a high purity starting point for building a transistor and is also the basis of the strain engineering in a modern process.
Since holes… Read More
System Reliability Audits
How reliable is your cell-phone? Actually, you don’t really care. It will crash from time to time due to software bugs and you’ll throw it away after two or three years. If a few phones also crash due to stray neutrons from outer space or stray alpha particles from the solder balls used in the flip-chip bonding then nobody… Read More
From Layout Sign-off to RTL Sign-off
This week, I had a nice opportunity meeting Charu Puri, Corporate Marketing and Sushil Gupta, V.P. & Managing Director at Atrenta, Noida. Well, I know Sushil since 1990s; in fact, he was my manager at one point of time during my job earlier than Cadence. He leads this large R&D development centre, consisting about 200 people… Read More
Any MIPI CSI-3 Host IP Solution for SoCs Interfacing with Sensors?
For those taking a quick look at the various MIPI Interface specification, the first reaction is to realize that they will have to look at MIPI more closely, and that it will take them longer than expected to make sure they really understand the various specifications! Let’s start with the PHY. One specification defines the D-PHY,… Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival