Alchip is Paving the Way to Future 3D Design InnovationAt the recent TSMC OIP Ecosystem Forum in…Read More
GaN HEMT modeling with ANN parameters targets extensibilityDesigners choosing gallium nitride (GaN) transistors may face…Read More
AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 - China & Delays & CHIPS Act?- AMAT has OK QTR but outlook below…Read More
More Headwinds - CHIPS Act Chop? - Chip Equip Re-Shore? Orders Canceled & Fab Delay- CHIPS Act more likely to be maimed…Read More
Wally Rhines’s keynote at the ARM TechCon was about differentiation and how to use it to create measurable value. We all know what differentiation means in some intuitive sense, but how do you make it measurable? Wally’s answer was that differentiation is a measure of the difficulty of switching suppliers and is best… Read More
Every analog designer needs a foundry PDK (Process Design Kits) and EDA tools to design, layout and verify their AMS chip or IP. This week I had a chance to conduct an email interview with Taek-Soo Kim, VP of Technical Engineering at Dongbu HiTek in Korea. This specialty foundry supplies analog silicon worldwide.
Interview
Q: Tell… Read More
Introduction from Hezi Saar: Eric’s latest viewpoints and reports are host onIPnestas well as on Semiwikiand you can find information related to various Interface IP: USB 3.0, PCIe, SATA, DDRn, MIPI, HDMI and more.
Q: Eric, give us a quick introduction about your background as it relates to interface IP
A: I have spent 20 years working… Read More
By Carey Robertson, Director of Product Marketing, Mentor Graphics
IC physical verification requires a number of different types of checking, the most familiar being design rule checking (DRC), layout vs. schematic (LVS) checking, and parasitic extraction combined with circuit simulation. Fundamentally, it does not matter… Read More
This was my first ARM TechCon, they cordially invited me as media, but it certainly was not what I expected. Making matters worse, I had literally just flown in from a very long weekend sailing in Mexico which was much more interesting and certainly made me much less tolerant of sales and marketing nonsense. My Uncle Jim lives on a sailboat… Read More
Synopsys Journal is a quarterly publication for management dedicated to covering the latest issues facing designers today. It has been published now for two and a half years. Of course, you can go here and, once registered, get a copy of the journal.
But people don’t have a lot of time to read a journal like this so it has been … Read More
One of the challenges of designing a modern SoC is that the digital parts of the circuit are really something that in an ideal world you’d keep as far away from the analog as possible. The digital parts of the circuit generate large amounts of noise, especially in the power supply and in the substrate, two areas where it is impossible… Read More
The TSMC OIP conference was Monday and Tuesday of last week. You have probably NOT read about it since it was invitation only and press was not invited. Slides were not made available (except for Mentor), no photos or video were allowed, it was a very private affair. Given that, I won’t be able to go into great detail but I will give you… Read More
It is hard not to be impressed by Intel’s stunning financial performance since the 2008 downturn. They are on track to post revenue of $55B this year or 50% higher than 2008 while nVidia and AMD will be flat to less than 10% better. More significantly, earnings will be 3X that of 2008. More significantly, in the past 12 months they have… Read More
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
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