Breaking the Clock Lane Barrier: MIPI C-PHY/D-PHY Combo IP on TSMC N2PThe transition to advanced process nodes is reshaping…Read More
John Barr: The EDA Veteran and Award-Winning Needham Funds Portfolio ManagerJohn Barr, Portfolio Manager of the top-ranked Needham…Read More
Why Generic LLMs Fall Short for Critical Engineering DocumentationEngineering documentation has always been difficult to produce,…Read More
Re-Spins Get You Fired, Says Intel CEO Lip-Bu TanIntel CEO Lip-Bu Tan’s statement that “re-spins get…Read More
Caspia's AI Makes You a Security Verification ExpertLet’s face it, powerful, highly trained AI is…Read More
Harish Aepalais part of the Design Closure Methodology group at LSIand he recently talked about his ASIC handoff experience in a webinar. Harish works with logic and physical synthesis, timing constraints, RTL analysis and formal verification.
One challenge with ASIC handoff has been getting through design closure with the… Read More
I should start by saying that SEMI Smart Technology is not technology that is only half as smart as our phones, it is a conference on smart technology organized by SEMI. Officially it is called the International Technology Partners Conference with a sort of subtitle of From Smart Cars to Smart Cities: Shaping the Future of Microelectronics… Read More
The company Nvidiais synonymous with designing all things video and GPU, so I watched Ting Ku, director of engineering at an archived webinar today talk about: Comprehensive Layout-based ESD Check Methodology with Fast Full-chip Static and Macro-level Dynamic Solutions.… Read More
Since Imagination’s acquisition of MIPS at the end of last year, the MIPS product line has been given a new lease of life. There are two things driving this. The first is simply that with its new home, the MIPS architecture has a solid future whereas before it was uncertain. Secondly, Imagination moved their own general purpose… Read More
I just read this very interesting article posted by Kurt Shuler from Arteris, describing the “History of SoC Interconnect Fabric” and explaining why the SC industry needs an advanced approach, named the “fourth phase of the Interconnect Fabric history” in the article. Kurt’s point of view is that in the past the SoC interconnect… Read More
Switched-capacitor (SC) circuits are ubiquitous in CMOS mixed-signal ICs. Thermal noise, introduced by MOS switches and active amplifier circuitry, is the major performance limiter in these circuits. This webinar reviews analysis techniques to accurately analyze the noise performance of switched-capacitor circuits … Read More
The foundry executive shuffle continues at Samsung, GlobalFoundries, and TSMC. Some expected, some not, the needs of the many outweigh the needs of the few. As I have mentioned before I have no inside knowledge as to who will be named as Dr. Morris Chang’s successor but here is my candidate for the next TSMC CEO.
First, the executive… Read More
The EDA tool space has been booming in this new “mobile era” of computing. As the world transitions to system-on-chip design methodologies, and as more teams are developing even more products for an ever-broadening set of end markets, the demand for ever more sophisticated design tools has only continued to skyrocket.… Read More
This is a live Silicon Valley event and yes there is such a thing as a free lunch. This is the first in a series of live SemiWiki collaborative events. I strongly believe that, especially in the age of social media, real world experience is key to the collaboration required to be successful in modern day semiconductor design. This is… Read More
In the spring of 1984, Mark Flomenhoft, Ph.D., approached Aki Fujimura, Randy Smith, and Steve Teig, to join him in developing a business plan to create a new EDA place and route (P&R) company. The three young software engineers all worked at Trilogy Systems Corporation where Mark was a director in the design automation department.… Read More
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Intel: Pushing EMIB Forward: Design Methodology Insights with Synopsys Tools