Primarius 2B

Xilinx Programmable Packet Processor

Xilinx Programmable Packet Processor
by Paul McLellan on 10-17-2012 at 5:19 pm

At the Linley conference last week I ran into Gordon Brebner of Xilinx. He and I go a long way back. We had adjacent offices in Edinburgh University Computer Science Department back when we were doing our PhDs and conspiring to network the department’s Vax into the university network over a two-week vacation. We managed to … Read More


8 Reasons Why I Hate My iPhone 5

8 Reasons Why I Hate My iPhone 5
by mbriggs on 10-17-2012 at 8:05 am

images?q=tbn:ANd9GcQrge1L1VKsYlHk14HvfapvlesjacXWpRugIVWGe3UHaTVWjT1P

Not really, but I regret upgrading from my Verizon based HTC Incredible to the iPhone 5. If you are on the fencebetween and iPhone 5 and a Samsung S3, consider reading this post.

I’ve been an anti Apple fan boy of sorts for the duration, but have gradually been sucked into the Apple eco system. I really like my iPad (3) and my “recliner … Read More


IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…

IP-SoC 2012 Conference: don’t miss keynotes talk from Cadence, Synopsys, STMicroelectronics…
by Eric Esteve on 10-17-2012 at 4:47 am

… Mentor Graphics, Design & Reuse or Gartner. The IP-SoC conference in Grenoble has been the very first 100% dedicated to Design IP, created by Gabriele Saucier 20 years ago, when “reuse” was more a concept than a reality within the design teams, and when Design IP was far to be a sustainable business.

Pr Gabriele Saucier had the… Read More


12m FPGA prototyping sans partitioning

12m FPGA prototyping sans partitioning
by Don Dingee on 10-16-2012 at 9:30 pm

FPGA-based prototyping brings SoC designers the possibility of a high-fidelity model running at near real-world speeds – at least until the RTL design gets too big, when partitioning creeps into the process and starts affecting the hoped-for results.

The average ASIC or ASSP today is on the order of 8 to 10M gates, and that includes… Read More


ReRAM Cell Modeling and Kinetics

ReRAM Cell Modeling and Kinetics
by Ed McKernan on 10-16-2012 at 8:55 pm

Introducing the first ReRAM-Forum movie!! In part 2 of their recently published papers in the Transactions on Electron Devices of the IEEE, Professor Ielmini’s group describe the modeling of resistive switching in bipolar metal oxide ReRAM. Like part 1, the paper is collaboration with David Gilmer of Sematech who provided the… Read More


Current Timing Closure Techniques Can’t Scale – Requires New Solution

Current Timing Closure Techniques Can’t Scale – Requires New Solution
by Daniel Nenni on 10-16-2012 at 8:30 pm


There’s a nice article on timing closure by Dr. Jason Xing, Vice President of Engineering at ICScape Inc. on the Chip Design website. Not familiar with ICScape? Paul McLellan called ICScape the The Biggest EDA Company You’ve Never Heard Ofand Daniel Payne did Schematic, IC Layout, Clock and Timing Closure from ICScape atRead More


Altera’s Real Impact with ARM based SOC FPGAs

Altera’s Real Impact with ARM based SOC FPGAs
by Ed McKernan on 10-16-2012 at 8:15 pm

At the annual Linley Processor Conference this past week a number of chip vendors proposed a raft of new networking solutions directed at solving today’s bandwidth issues. Perhaps the overall highlight of the conference was the recognition by Keynote Speaker Linley Gwennap of the shift that is taking place towards ARM based solutions.… Read More


Laker3 in TSMC 20nm Reference Flow

Laker3 in TSMC 20nm Reference Flow
by Paul McLellan on 10-16-2012 at 8:10 pm

SpringSoft, soon to be part of Synopsys but officially still a separate company for now, just announced that Laker[SUP]3[/SUP], the third generation of their layout product family, is featured in TSMC’s 20nm Custom Reference Flow.

Laker 20nm advancements include new double patterning-aware design and voltage-dependent… Read More


Kaufman Award Dinner at 50th DAC in Austin

Kaufman Award Dinner at 50th DAC in Austin
by Paul McLellan on 10-16-2012 at 8:05 pm

In past years the Kaufman award, the most prestigious in EDA, has been announced around September and presented during a dinner in October or November in Silicon Valley. EDAC and CEDA, the sponsors of the award, have just announced that this time the award dinner will take place in Austin at the 50th DAC following the early Sunday … Read More