As you all know I am a big fan of the ASIC business model. It was critical in the transformation of the fabless semiconductor industry and still plays a critical part in our success. In fact, the ASIC business model is leading the way for systems companies to make their own chips. Remember, Apple started with the ASIC business model … Read More
Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUsFor decades, high-performance CPU design has been dominated…Read More
Orchestrating IC verification: Harmonize complexity for faster time-to-marketBy Marko Suominen and Slava Zhuchenya of Siemens…Read MoreBasilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status QuoAt Hot Chips 2025, Philippe Sauter of ETH…Read More
GlobalFoundries 2025 Update GTS25"GTS25 brings together leaders from across the semiconductor…Read More
Verifying Design for In-Car Networks
Once upon a time the role of electricity in a car was pretty modest: spark plugs, alternator, lighting, some simple instrumentation and maybe heating, all supported by an equally simple wiring harness (my wife has a 1962 Morris Minor, so I know exactly what the whole wiring harness looks like). How times have changed. Now most or … Read More
On-Chip Power Distribution Networks Get Help from Magwel’s RNi
Counting squares is a useful tool for calculating simple resistance in wires, but falls short in reality when wires deviate from ideal. Frequently the use of RC extraction tools for determining resistance in signal lines in digital designs can be effective and straightforward. However, there are classes of nets in designs that… Read More
An Easy Path to Bluetooth 5-enabled SoC Design
Bluetooth (BT) was never a bit-player in communication but what surprised me is that is already dominating the market, at least as measured by radios sold, and is likely to extend that lead over the next 5 years. Particularly impressive is that BT already leads cellular and WiFi. This strength is certainly influenced by sales into… Read More
SPIE Advanced Lithography and Synopsys!
SPIE is the premier event for lithography held in Silicon Valley and again Scotten Jones and I will be attending. EUV is generally the star of the show and this year will be no different now that TSMC has committed to EUV production in 2019.
Last year at SPIE, TSMC presented the history of EUV development from the beginning in 1985 as … Read More
Finding Transistor-level Defects Inside of Standard Cells
In the earliest days of IC design the engineering work was always done at the transistor-level, and then over time the abstraction level moved upward to gate-level, cell-level, RTL level, IP reuse, and high-level modeling abstractions. The higher levels of abstraction have allowed systems to be integrated into an SoC that can… Read More
Computability 2.0?
There’s muttering among computing fundamentalists that perhaps we ought to revisit the definition of computability given recent advances in methods of computing, especially machine learning and quantum computation.
Computability is about what can and cannot be computed, either by a human or non-human computer. This is a … Read More
Four Steps for Logic Synthesis in FPGA Designs
I remember meeting Ken McElvain at Silicon Compilers for the first time back in the 1980’s, he was a gifted EDA tool developer that did a lot of coding including logic synthesis, a cycle-based simulator and ATPG. Mentor Graphics acquired Silicon Compilers with Ken included, and he continued to create another logic synthesis… Read More
CEO Interview: David Dutton of Silvaco
Silvaco has undergone one of the most impressive EDA transformations so it was a pleasure to interview the man behind it. David Dutton’s 30+ year career started at Intel, Maxim, and Mattson Technology where he led the company’s turnaround and finished as President, CEO, and board member. David joined Silvaco as CEO… Read More
ISS Gary Patton Keynote: FD-SOI, FinFETS, and Beyond!
Two weeks ago the SEMI ISS Conference was held at Half Moon Bay in California. On the opening day of the conference Gary Patton CTO of GLOBALFOUNDRIES gave the keynote address and I also had the chance to sit down with Gary for an interview the next day.
Intel’s Pearl Harbor Moment