Webinar: RF design success hinges on enhanced models and accurate simulationTraditional RF board design strategies based on circuit…Read More
Arteris Raises Bar Again with AI-Based NoC DesignModern semiconductor devices, a far cry from the…Read More
2025 Outlook with Veerbhan Kheterpal of QuadricQuadric Inc. is the leading licensor of general-purpose…Read More
Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignConThere were many announcements and significant demonstrations of…Read More
Discussion on design metrics tends to revolve around power, performance, safety, and security. All of these are important, but there is an additional performance objective a product must meet defined by a minimum service level agreement (SLA). A printer display may work fine most of the time yet will intermittently corrupt the… Read More
At the DesignCon 2023 event this year there was a presentation by Micron all about DDR5 design challenges like the need for a Decision Feedback Equalizer (DFE) inside the DRAM. Siemens EDA and Micron teamed up to write a detailed 25 page white paper on the topic, and I was able to glean the top points for this much shorter blog. The DDR5… Read More
Many credible market analysis firms are predicting the semiconductor market to reach the trillion dollar mark over the next six years or so. Just compare this to the more than six decades it took for the market to cross the $500 billion mark. The projected growth rate is incredible indeed and is driven by fast growing market segments… Read More
As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering… Read More
Current 1a-DRAM and 5/4nm foundry nodes have minimum pitches in the 28 nm pitch range. The actual 28 nm pitch patterns are one-dimensional active area fins (for both DRAM and foundry) as well as one-dimensional lower metal lines (in the case of foundry). One can imagine that, for a two-dimensional routing pattern, both horizontal… Read More
Dan is joined by Al Neves, Founder and Chief Technology Officer at Wild River Technology. Al has 30 years of experience in design and application development for semiconductor products and capital equipment focused on jitter and signal integrity. He is involved with the signal integrity community as a consultant, high-speed… Read More
Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.
As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about.
Post-quantum cryptography (PQC) might be a lower priority for many organizations, with the specter of quantum-based cracking seemingly far off. Government agencies are fully sensitized to the cracking risks and the investments needed to mitigate them and are busy laying 10-year plans for migration to quantum-safe encryption.… Read More
S2C has been shipping FPGA prototyping platforms for SoC verification for almost two decades, and many of its customers are developing SoCs and silicon IP for Bluetooth applications. Prototyping Bluetooth designs before silicon has yielded improved design efficiencies through more comprehensive system validation, and… Read More
The semiconductor industry has been responding to increasing device complexity and performance requirements in multiple ways. To create smaller and more densely packed components, the industry is continually advancing manufacturing technology. This includes the use of new materials and processes, such as extreme ultraviolet… Read More
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Rethinking Multipatterning for 2nm Node