How Cadence is Building the Physical Infrastructure of the AI EraAt the 2025 NVIDIA GTC Conference, CEO Jensen…Read More
Andes RISC-V CON in Silicon Valley OverviewRISC-V conferences have been at full capacity and…Read More
Achieving Seamless 1.6 Tbps Interoperability for High BW HPC AI/ML SoCs: A Technical Webinar with Samtec and SynopsysHPC Bandwidth Explosion and 1.6T Ecosystem Interop Need…Read More
A Perspective on AI Opportunities in Software EngineeringWhatever software engineering teams are considering around leveraging…Read More
The semiconductor ecosystem is changing. Monolithic design is becoming multi-die design. Processors no longer inform software development options. It’s now the other way around with complex AI software informing the design of purpose-built hardware. And all that special-purpose hardware needs drivers to make it come to … Read More
What’s new in debugging multi-/many-core systems? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.
This month’s pick is Post-Silicon… Read More
Tell us a little bit about yourself and your company.
I am Rui Tang, co-founder and VP of MSquare Technology. With a Ph.D. in Computer Engineering from Northeastern University and a master’s degree in management science and engineering from Stanford University, I bring over 23 years of experience in the IC industry. Prior to MSquare,… Read More
Last week, Synopsys announced an expansion of their Hardware-Assisted Verification (HAV) portfolio to accelerate semiconductor design innovations. These advancements are designed to meet the increasing demands of semiconductor complexity, enabling faster and more efficient verification across software and hardware… Read More
Artificial intelligence and machine learning have undergone incredible changes over the past decade or so. We’ve witnessed the rise of convolutional neural networks and recurrent neural networks. More recently, the rise of generative AI and transformers. At every step, accuracy has been improved as depicted in the graphic… Read More
The dominance of GPUs in AI workloads has long been driven by their ability to handle massive parallelism, but this advantage comes at the cost of high-power consumption and architectural rigidity. A new approach, leveraging a chiplet-based RISC-V vector processor, offers an alternative that balances performance, efficiency,… Read More
Whether EUV or DUV doesn’t matter at 20 nm pitch
The International Roadmap for Devices and Systems, 2022 Edition, indicates that the “2nm” node due in 2025 (this year) has a minimum (metal) half-pitch of 10 nm [1]. This is, in fact, less than the resolution of a current state-of-the-art EUV system, with a numerical aperture… Read More
– NIST to lose 100’s of mainly CHIPS Act people
– If no people are left to administer CHIPS Act it dies by default
– Following USAID play book to kill an unwanted program
– Using the “probationary” clause as excuse to fire recent CHIPS hires
Dan is joined by Sebastien Clamagirand, Global Senior Vice President of Automotive System Engineering and Marketing at NXP Semiconductors. Sebastien focuses on system solutions for vehicle architectures that support the shift to software-defined vehicles. Under his leadership, NXP delivers pre-integrated, scalable … Read More
William Wang is the CEO and founder of Alpha Design AI, a generative AI startup transforming chip design and verification through ChipAgents, an agentic AI development tool for RTL and verification engineers. ChipAgents accelerates design, debugging, and verification of hardware description languages (HDL), integrating… Read More
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TSMC 2025 Technical Symposium Briefing