RTL Design Engineer

Job Responsibilities

• Analysis of Video Codec Standards and Video Input/Output Specifications/Algorithms

• Architecture Design for HW IP Implementation

• Macro Architecture: System requirements-based structural design, control flow definition, and test scenario definition

• Micro Architecture: Designing a specific structure at the sub-block level

• Develop and verify RTL (Module), Testbench, and Script compatible with PPBA

• Function verification and debugging, performance optimization (Performance / Power / Bandwidth / Area)

Essential requirements

• Verilog / SystemVerilog / Python-based design, verification, and debugging skills

• Able to understand and modify C code

• Understanding HW ASIC IP / SoC / FPGA Design Flow and EDA Tools
Benefits

• Understanding Video Codec Standards

• Experience in hardware design and verification using AI tools
Working environment and welfare

• Flexible working hours (Core time 11:30 ~ 15:30)

• Lunch/Dinner Support

• Provides 3 million won in optional employee benefits per year

• Refreshment vacation and vacation allowance

• Annual health checkups worth 700,000 won provided

• Support for enhancing development capabilities, such as promoting in-house seminars

• Use an English nickname

• Starting annual salary of 50 million won for a bachelor’s degree