RTL Design and Verification Engineer

Job Responsibilities

• Design (RTL coding), verification (simulation and synthesis), and maintenance of value-added functions of developed HW IP

• Setup of verification environment and debugging for HW IP under development

• Customer support for the completed product

Essential requirements

• Graduation (Bachelor’s or Master’s) from a related major, such as Electronics (Engineering) or Semiconductor Engineering

• Possess basic knowledge of Verilog & C

• 5 to 12 years of experience

Benefits

• Possesses knowledge of Python/Perl/JAVA/Shell Script

• Possess knowledge of video codecs

• Experience in FPGA Development Environment

• Proficient in English

Working environment and welfare

• Flexible working hours (Core time 11:30 ~ 15:30)

• Lunch/Dinner Support

• Provides 3 million won in optional employee benefits per year

• Refreshment vacation and vacation allowance

• Annual health checkups worth 700,000 won provided

• Support for enhancing development capabilities, such as promoting in-house seminars

• Use an English nickname

• Starting annual salary of 50 million won for a bachelor’s degree