Mask Layout Designer III

Job Title: Mask Layout Designer III

Client: Apple

Location: Cupertino, CA, 95014

Position Type: Contract – 11 Months -needed (onsite first 2 weeks in role, then allowed to work remotely)

Job ID: 36005540

Job Summary:

 

Layout Engineers are responsible for delivering Analog Mixed-Signal layouts.

 

They collaborate with client Layout/schematic DRIs of highly skilled individuals to develop world-leading SOCs. As a part of the AMS layout team, you will be delivering fully-verified, layout. This includes the following: Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies. Reviewing and analyzing floor plans and intricate circuits. Running complete sets of design verification tools available on AMS blocks. Working with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Applying sophisticated CAD tools and mask design knowledge to deliver accurate and robust layout that matches performance, area and power requirements..

 

 

 

Responsibilities

 

• Responsible for mask layout of analog designs for integration into a System-on- Chip (SoC).

 

• Independently interacting with circuit designers or layouts leads to understanding layout requirements to meet circuit performance requirements.

 

• Assess, plan, and execute as required to meet schedule deadlines and communicate potential problems to circuit designer or layout lead.

 

• Work with other custom analog layout designers and ensure quality of work is meeting standards required by circuit design or layout lead.

 

Required Skills:

 

• Layout design of tight matching, low noise, and low power analog blocks, resistors, capacitors, pad IOs, and ESD structures.

 

• IR drop, RC delay, electromigration, self-heating, and cross capacitance.

 

• 3CALIBRE DRC, ERC, and LVS reports.

 

• Analog/mixed-signal layout design of SubMicron CMOS circuits.

 

• Recognizing failure prone circuit and layout structures; and

 

• Analog and DFM best practices.

 

 

 

Preferred Qualifications:

 

• 5+ years of experience in analog/mixed-signal layout design, with a focus on deep sub-micron CMOS circuits and at least 2+ years in FinFET technologies

 

• Excellent communication skills and able to work with multi-functional teams

 

• Familiar with CAD tools like Virtuoso, Innovus, Calibre is a plus

 

• Programming knowledge in SKILL, Perl, and/or Python is a bonus

 

• Concentration in Mixed-Signal and RF Integrated Circuits is helpful

 

 

 

Education:

 

• Bachelor’s degree or foreign equivalent in Electrical Engineering, Alternatively, employer will accept a Master’s degree or foreign equivalent Electrical Engineering, Electronic Engineering, or related field and 3 years of progressive, post-baccalaureate experience in the job offered or related occupation.