- Demonstrated skills at understanding customer needs and identifying solutions to their challenges with Cadence digital design tools
- Exposure to digital IC design and experience in applying solutions in the RTL-GDSII digital space
- Demonstrated ability in customer tool debug and usage issues (on-site and remote)
- Past direct experience with either CDNS or equivalent competitive digital design tools
- Outstanding oral communication skills to deliver customer and marketing presentations, product updates, etc.
- Close collaboration with R&D on issues using established protocols
- Communicate with customers on issue workarounds and new tool fixes
- Participate in customer benchmark activities and pre-release code bashing with DSG products
- On-site customer “office hours,” when local, is a MUST-HAVE
The candidate must have demonstrated experience in several of the following areas:
- RTL Synthesis/Physical Synthesis
- Design constraint creation (SDC) & debug
- Static timing analysis, Power Analysis (Static, Dynamic, Leakage)
- Timing optimization, in logical and physical mode
- Low power implementation with knowledge of UPF/CPF
- CAD flow develop/debug/optimize
- Scripting experience with: TCL, PERL
– The candidate will have broad knowledge experience in the physical design process of modern SOCs (28nm or below).
– The candidate will possess a self-starter mindset with an established track record of complex problem solving in SOC physical design.
– The candidate should possess excellent communication skills and be adept at working with both customer engineers/mgmt. as well as Cadence team members
-MS or BS Computer/Electrical Engineering with 5-10 years experience
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To view the job application please visit cadence.wd1.myworkdayjobs.com.