DFT Engineer

Job Summary :-  A DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor designs are testable, high-quality, and manufacturable, while balancing coverage, performance, power, and cost.

 

Key Skills:

Ø    End-to-end DFT implementation

Ø    Scan insertion & compression, ATPG

Ø    MBIST, LBIST, JTAG/Boundary Scan

Ø    DFT signoff, fault coverage, debugging

Ø    RTL, SoC design flow, STA

Ø    Tools: Siemens Tessent, Synopsys TestMAX, Cadence Modus

Ø    Scripting: TCL, Python, Perl

Please share your resume to shanmukeshwari.b@makonissoft.com

Key Responsibilities

 

1.  DFT Architecture G Strategy

·        Define and implement DFT architecture at block/IP or SoC level

·        Specify test methodologies (scan, MBIST, boundary scan, compression)

·        Ensure testability built early into RTL design flow

·        Balance trade-offs between coverage, area, power, and test time

2.  DFT Implementation Perform:

·        Scan insertion and stitching

·        ATPG pattern generation and simulation

·        MBIST / LBIST / boundary scan integration

·        Develop and validate DFT timing constraints (STA)

·        Execute DFT flows at RTL and gate level

3.  Test Coverage G Ǫuality

·        Analyze and improve fault coverage

·        Debug scan/ATPG issues and resolve coverage holes

·        Optimize:

o   Pattern count

o   Test cost

o   Test time

4.  Verification G Signoff

·        Run DFT verification and DRC checks

·        Ensure clean DFT signoff (coverage, timing, power impact)

·        Validate patterns using simulation and test tools

·        Support DFT integration guidelines at SoC level

5.  Cross-Functional Collaboration Work with:

·        RTL design

·        Physical design (PD)

·        Verification