Design Verification Intern – Ncore 2025

Website ArterisIP
Description
Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.
Key Responsibilities:
- Test environment automation using scripting language (TCL/Python/Java-Script)
- Testcases creation, checkers, assertions, coverage using System-Verilog and UVM methodology
- Run test cases, debug failures for root cause.
Experience Requirements / Qualifications:
- Run test cases, debug failures for root cause.
- Debugging skills, fast learner and motivated to learn new things like UVM, Verilog, System-Verilog…etc.
- Excellent written and oral communication skills.
Education Requirements:
Estimated Base Salary:
- $80 to $95 per hour
About Arteris:
Arteris is a leading provider of system IP for the acceleration of system-on-chip (SoC) development across today’s electronic systems. Arteris network-on-chip (NoC) interconnect IP and SoC integration automation technology enable higher product performance with lower power consumption and faster time to market, delivering better SoC economics so its customers can focus on dreaming up what comes next.
With over 250 employees with headquarters in Silicon Valley and offices around the globe, we are a catalyst for SoC innovation so companies ranging from startups to the biggest technology market leaders can effectively create new products with proven connectivity flexibility and ease. Learn more at arteris.com.
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To view the job application please visit www.arteris.com.
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