Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.
- Bachelor degree with 5+ years of applicable experience, Master degree with 3+ years of applicable experience in electrical engineering, microelectronics.
- Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
- Solid knowledge on Low Power Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
- Successful track records of taping out complex chips at various technology nodes. Experience with advanced nodes at 16nm and below is preferred.
- Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
- Self-motivated, able to work as a team player, excellent verbal and written communication skills in English.
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To view the job application please visit cadence.wd1.myworkdayjobs.com.