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Design Engineer

Design Engineer
by Admin on 06-02-2020 at 9:04 pm

  • Full Time
  • Nanjing

Website Cadence

  • Implement and optimize hard-macro/ full-chip to achieve aggressive low power, area and timing goals
  • DFT Insertion
  • Delivery of timing clean, logically equivalent netlists to physical design team
  • Lead hard-macro/full-chip timing closure
  • Implement both functional ECO and timing ECO

Requirements:

  • Experience in RTL design, synthesis and STA
  • Good understanding of physical design concepts: floorplan, placement, congestion and timing closure
  • Familiar with multi power domain designs is a plus
  • Experience in DFT is a plus
  • Good tcl, perl scripting skills
  • Ability to collaborate effectively with other function teams and strong written and verbal communication skills
Apply for job

To view the job application please visit cadence.wd1.myworkdayjobs.com.

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