ASIC Digital Design Engineering Intern

Key Program Facts:

• Program Length: This internship will last for a duration of 16 months for Undergraduate (Bachelor’s) students. Duration can be flexible for Master’s students.
• Location: Nepean, Ontario, Canada
• Working Model: Onsite
• Full-Time/Part-Time: Full-Time
• Start Date: May 2025

What You’ll Be Doing:

• Designing and verifying next-gen Ethernet, PCIe, USB SERDES and controller products. Delivering high-performance silicon IP.
• Writing and refining Verilog/SystemVerilog code.
• Creating testcases and writing assertions.
• Participating in design reviews.
• Contributing to cutting-edge digital or mixed-signal IPs.

What You’ll Need:

• Experience in Verilog/SystemVerilog/VHDL.
• Understanding of digital design.
• Knowledge of high-speed digital and mixed-signal design is a plus.
• FPGA design experience.
• Experience with digital signal processing is a plus.