It’s Now Time for Smart Clock Networks

By now most SoC designers are pretty familiar and comfortable with the use of Network on Chip (NOC) IP for interconnecting functional blocks. Looking at the underlying change that NOCs represent, we see the use of IP to supplant the use of tools for implementing a critical part of the design. The idea that ‘smart’ things are better than just structural implementation is a ubiquitous theme in our lives. Smart bulbs, smart appliances, smart thermostats, smart doorbells all make for better performance and functionality once the technology became available. The time has now come for on-chip clocking to take advantage of a smart approach through the use of IP and a new architecture to replace fixed clock trees and meshes found in previous generations of designs.

Clock networks have always been a challenging area for IC design. While they are often regarded as an unseen part of any design, they consume a significant percentage of chip power and take up considerable real estate. On top of this they are a critical factor in proper chip functionality and performance. Though for years they have been a neglected area in design flows. Movellus, a provider of clock solutions, is taking a fundamentally new approach to clock design. Instead of building a fixed clock tree out of unintelligent buffers, wires and PLLs, they use a set of intelligent IP blocks to handle the major issues encountered in clock design, skew, gating, OCV, power integrity and more.

The capabilities of the Movellus Maestro Clock Network solution is nicely summarized in a paper authored by Linley Gwennap Principal Analyst and Aakash Jani Senior Analyst with the Linley Group. The paper titled “Movellus Maestro: An Intelligent Clock

Network” explains the motivation for applying an IP based solution to clock generation and covers the benefits that result.

Historically clock networks have either been clock trees or meshes or a hybrid. Each has their own advantages and trade-offs. Clock trees tend to use less power but are subject to clock skew. Meshes reduce skew but come with an increase in power consumption. Maestro blends the two with the addition of intelligent IP that monitors skew caused by a variety of factors such as supply voltage fluctuations, OCV and temperature.

By virtually eliminating Skew and PVT effects higher operating frequencies can be obtained. Movellus cites some examples where usable clock periods have increased by up to 44%, allowing for much higher Fmax. Another phenomenon that Maestro manages is voltage droop when blocks are toggled on and off to conserve system power. Normally as blocks are switched on when needed there is a latency period while the power rails recover from the additional load. The Maestro Adaptive Workload Module (AWM) reduces this latency by managing clock speeds, allowing in higher system performance.

Maestro reduces the effects of OCV and power jitter on the clock by constantly monitoring and adjusting the clock network. This is especially important at near threshold voltages found in IoT devices. With proper management of OCV and jitter, margins can be reduced to improve performance and power. Maestro also employs a clever system that distributes the operation of the clock subsystems across different phases to spread out simultaneous switching IR impact from clock operation. This reduces overall power consumption and allows for improved performance.

The Linley paper covers additional details and other features of the Movellus Maestro Clock Network. It’s about time that clocks became an area for innovation. Traditionally the major players in EDA have not devoted resources to radically rethinking this crucial component of all SOCs. In a way it is surprising, given the hugely important role that clock distribution plays. The paper is available to read as a download from the Movellus website.

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