How much IP & reuse in this SoC?

According with the survey from GSA-Wharton design IP blocks reuse in a new IC product is 44% in average. Looking at the latest Wireless platform from TI, OMAP5, we have listed the blocks which have been (or will be) reused, coming from internal (or external) IP sourcing. For a license cost evaluation of -at least- $10M!

For those who missed the information, the latest wireless platform, or application processor from TI, has been announced last month. This true System on Chip has been designed in 28nm technology, and includes no less than four processor core (two ARM Cortex-A15 and two Cortec-M4), one DSP core (TI C64x) and multiple image and audio dedicated processors, to mention only pure computing power. All these core are clearly IP, whether they comes from ARM, Imagination Technologies or TI himself. The M-Shield system security technology, as being initially introduced by TI is more an internally developed function, being enhanced (crypto DMA added) and re-used from previous generation (OMAP4) , as well as the Multi-pipe display sub-system. So far, all these blocks are IP or reused functions.

Let’s take a look at the Interface blocks, including external memory controllers and protocol based communication functions, these are strong candidates for IP sourcing or internal reuse:
·Two LPDDR2 Memory Controllers (EMIF1, EMIF2)
·One NAND/NOR Flash memory Controller (GPMC)
·One Memory Card Controller (MMC/SD)
·To my knowledge, the first time in a wireless processor, a SATA 2.0storage interface (a PHY plus a Controller)
·For the first time on OMAP family, a SuperSpeed USB OTG, signing USB 3.0 penetration of the wireless handset market (USB 3.0 PHY plus a Dual Mode OTG Controller)
·More usual is the USB 2.0 Host, but the function is by 3 (USB 2.0 PHY plus a Host Controller)
·For the MIPI functions, the list of supported specifications is long:oLLI/uniport to interface with a companion device in order to share the same external memory and save a couple of $ on each handset (MIPI M-PHY and LLI controller)
oTo interface with the Modem, another LLI (same goal as above?) and two HSIfunctions (High Speed Synchronous Link, a legacy functions to be probably replaced by DigRF in the future)
oTo interface with the various (!) cameras, one CSI-3 function (M-PHY, up to 5 Gbs, and CSI-3 Controller) and not less than three CSI-2 function (D-PHY, limited to 1 Gbs, and the CSI-2 Controllers)
oTo handle the Display, two DSI (D-PHY and the DSI Controllers)serial interfaces and one DBI (Bus Interface)
oAnd SlimBus, a low performance, serial, low power interface with Audio chips

·With HDMI 1.4a, we come back to a well known protocol used in PC and Consumer

I understand you start to be tired reading such a long list, so I will stop here for the moment. Interesting to notice: almost each of the above listed interface function would generate an IP license cost of about $500K (can be less or more). This assume an external sourcing, which is certainly not true for all the blocks. If we look now at the different processor cores, all except the DSP have to be licensed. The “technology license” paid by TI to ARM to use Cortex M-15 and M-4 weights several million dollars (even if the core can be reused in other IC). So, in total, the processing power used in OMAP5 has a 3 to $5M cost.

To be exhaustive, we have to add to this list of IP (or re-used blocks) all the Interfaces and I/Os (UART, GPIO, I2C and so on) not listed before as well as some high value blocks, like: embedded memory (L2 cache, L3 RAM), a Network on Chip Interconnect, more than one PLL… Maybe more.

If we look at the block diagram, we see that the IP or re-used blocks can match all the listed functions. Does that means that 100% of OMAP5 is made of IP? Certainly not, as the block diagram does not show the testability or the power management, essential part of this SoC. But an estimate of 80% of IP/Re-use, at a theoretical license cost in the range of $10M looks realistic for OMAP5.