The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem

During my frequent trips to Taiwan as a foundry relationship professional I remember meeting Frankwell Lin, CEO of Andes, in Taiwan 15+ years ago. As I walked to TSMC HQ from the Hotel Royal (my second home for many years) Andes was about mid point and Frankwell’s door was always open. Sometimes just tea, sometimes technology, there was always a reason to talk to Frankwell.

Throughout my career I have always been excited about open standards as a platform to accelerate design starts. The semiconductor industry is all about design starts, right? Having been involved with many different open standard initiatives, some they succeeded but failure was quite common. RISC-V however has been a resounding success and I am honored to be a part of it, absolutely.

The evolution of RISC-V, the rise of Andes Technology, and the emergence of the RISC-V Now! Conference illustrate how open hardware architectures are transforming the semiconductor industry. Together, they represent a shift toward open standards, collaborative ecosystems, and new approaches to building processors for modern computing workloads.

The story begins with the development of RISC-V, an open instruction set architecture (ISA) derived from the principles of RISC. Earlier RISC architectures emerged in the 1980s as a simpler and more efficient alternative to complex instruction set computing. While architectures like ARM became highly successful, they remained proprietary. RISC-V, created in 2011 at the University of California, Berkeley, introduced a new concept: an ISA that is open and free for anyone to implement, modify, and extend. This openness allows companies and researchers to build custom processors without paying licensing fees, accelerating innovation across industries.

Over the past decade, the architecture has rapidly grown from an academic project into a major industry platform used in microcontrollers, embedded systems, AI accelerators, and even data-center research. Analysts estimate the architecture is on track to power tens of billions of chips worldwide and has reached significant market penetration across multiple computing sectors.

A key contributor to this ecosystem is Andes Technology, a Taiwanese semiconductor company specializing in RISC-V processor IP. As a founding premier member of the global RISC-V community, Andes has played a central role in commercializing the open ISA. The company designs 32-bit and 64-bit processor cores that can be integrated into SoC designs for applications ranging from consumer electronics to automotive systems and AI computing. Its processor portfolio includes high-efficiency embedded cores and high-performance multiprocessor clusters, many of which support advanced features such as vector processing, digital signal processing, and customizable instruction extensions. These capabilities allow hardware designers to tailor processors to specific workloads, which is one of the most attractive features of the RISC-V model. Over time, Andes-powered processors have been integrated into billions of chips used around the world.

As RISC-V adoption grew, Andes also began investing in community-building events to accelerate collaboration across the ecosystem. One example is the Andes RISC-V CON, a series of conferences designed to bring together engineers, researchers, and technology companies working on RISC-V platforms. These events typically include keynote speeches from industry leaders, technical sessions on processor design, and discussions on emerging applications such as artificial intelligence, automotive electronics, and communications systems. Conferences often feature multiple tracks, including developer sessions where engineers can learn about debugging tools, vector extensions, and custom instruction development. By providing a space for collaboration and knowledge sharing, these events have helped strengthen the RISC-V ecosystem and encourage wider adoption of the architecture.

Building on the success of these earlier events, Andes launched the RISC-V Now! conference series in 2026. Unlike earlier conferences that focused primarily on the technology and ecosystem of the architecture, RISC-V Now! emphasizes real-world deployment and commercial implementation. The conference brings together system architects, semiconductor executives, and engineers who are already building and shipping products based on RISC-V processors. Topics typically include system-level design trade-offs, strategies for integrating CPUs into complex SoCs, software enablement challenges, and lessons learned from production deployments. The first events in the series were scheduled in several global technology hubs—including Silicon Valley, Hsinchu, Shanghai, and Beijing highlighting the global nature of the RISC-V movement.

The emergence of RISC-V Now! reflects a broader transition within the RISC-V ecosystem. Early adoption focused heavily on experimentation and research, but the current phase is centered on building commercial products and scalable computing platforms. As computing workloads grow more complex—especially in fields like artificial intelligence, automotive autonomy, and edge computing—companies are seeking processor architectures that offer flexibility, efficiency, and control. RISC-V provides these advantages by allowing designers to customize instructions, optimize for power or performance, and maintain full control over their hardware roadmap.

Bottom line: The evolution of RISC-V represents one of the most significant shifts in modern processor architecture. Andes Technology has played an important role in advancing this open hardware movement by providing commercial CPU IP and fostering community collaboration through conferences and ecosystem initiatives. The launch of the RISC-V Now! conference marks the next stage of this journey, focusing on real-world deployment and production systems. Together, these developments highlight how open architectures and collaborative innovation are reshaping the future of computing.

Also Read:

The Launch of RISC-V Now! A New Chapter in Open Computing

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

RISC-V: Powering the Era of Intelligent General Computing