Andes Technology: A RISC-V Powerhouse Driving Innovation in CPU IP

As it celebrates its 20th anniversary in 2025, Andes Technology stands as a defining force in the RISC-V movement—an open computing revolution. What began in 2005 as a bold vision to deliver high-efficiency Reduced Instruction Set Computing (RISC) processor IP has evolved into a company whose innovations power billions of devices worldwide. And Andes’ impact extends well beyond hardware. Through sustained investment in open-source software and active leadership in industry initiatives, the company has played a key role in strengthening the RISC-V ecosystem and ensuring seamless integration between architecture and software.

Frankwell Lin, Chairman and CEO of Andes Technology gave a keynote presentation at Andes RISC-V CON 2025. This annual conference, convened by Andes, has grown steadily in both attendance and speaker participation since its inception, reflecting the company’s increasing market adoption and growing influence on the technology front. The following is a synthesis of Lin’s talk.

Early Commitment to RISC-V

From the outset, Andes focused on delivering high-efficiency CPU IP based on the RISC philosophy. Its proprietary AndeStar™ ISA and development platform, AndeSight™ IDE, formed the technological bedrock for its early success, offering customers a flexible and scalable foundation for SoC design.

In 2016, Andes became a founding member of RISC-V International, well before the open ISA gained mainstream industry momentum. That same year, it was recognized by TSMC with a “New Partner of the Year” award, signaling the broader ecosystem’s confidence in Andes’ direction.

By 2018, Andes had crossed the threshold of one billion SoCs shipped with its CPU IP embedded. The company has since shipped more than 16 billion chips through its customers’ designs, with over two billion units delivered in 2024 alone.

From Innovation to Market Leadership

Andes introduced its first RISC-V processor IP in 2017, marking the beginning of a wave of technical innovation. It soon followed up with the industry’s first RISC-V Packed-SIMD CPU. The NX27V, the first commercially available RISC-V Vector CPU IP was adopted by Meta shortly after the IP was launched in 2019. These breakthroughs demonstrated that RISC-V could address high-performance computing needs as effectively as proprietary architectures.

The company’s momentum continued with the release of ISO 26262–compliant safety cores in 2022, followed by a multicore vector processor in 2023. In 2024, Andes became the first to introduce a RISC-V processor compliant with ISO 26262’s stringent ASIL-D safety requirements.

Today, Andes operates on a predictable release cadence, launching six new RISC-V cores each year to meet the needs of markets from AI to automotive. You can read about Andes full lineup of RISC-V processor solutions on a separate post on SemiWiki, soon.

Establishing RISC-V Standards: RVA23 and Beyond

Beyond its product offerings, Andes plays a leading role in the governance and evolution of the RISC-V ISA. As a member of the Board of Directors and Technical Steering Committee at RISC-V International, the company has helped shape major architecture extensions, including packed SIMD, matrix multiplication, fast interrupt handling, and IOPMP for memory protection.

A significant part of Andes’ commitment to standardization is its full alignment with the RVA23 profile, the recently ratified standard that defines a consistent set of features for 64-bit RISC-V application processors. This profile mandates support for key extensions such as vectors and virtualization, helping ensure consistency across platforms. Andes has already incorporated RVA23 compliance into its roadmap, further cementing its position as a leader in forward-compatible, ecosystem-ready processor IP.

Building the Software Foundation

Understanding that hardware alone isn’t enough, Andes has long invested in enabling software. The company is an active contributor and maintainer of several core open-source projects, including GCC, glibc, Linux, U-Boot, and SIMDe. It also supports broader ecosystem efforts through involvement in the RISE project, the Linux Foundation, and the Civil Infrastructure Platform, all aiming to strengthen RISC-V software infrastructure.

By engaging deeply with both the hardware and software layers, Andes ensures that its IP not only meets performance and power goals but also integrates seamlessly into modern toolchains and operating systems.

Sustained Growth and Global Reach

Following its IPO in 2017, Andes has delivered consistent growth with a compound annual revenue growth rate of 26.8 percent. In 2024, it recorded an impressive 30.6 percent growth—largely fueled by RISC-V, which now accounts for 92 percent of its license revenue. The company has signed more than 200 RISC-V commercial license agreements and operates six global design centers, supporting customers across North America, Asia, and Europe. It is the global market leader in RISC-V IP, with over 30% market share, as reported by market research firm, The SHD Group.

A New Identity for a New Era

In April 2025, Andes Technology unveiled a refreshed corporate logo as part of its 20th-anniversary celebrations. The new logo represents the company’s evolution and its commitment to innovation in the RISC-V ecosystem. The “S” in the new logo, stylized as a “5” reflects its alignment to the RISC-V open-standard movement. Alongside the rebranding, Andes announced the expansion of its headquarters, signaling its continued growth and dedication to serving a global customer base.

Looking Ahead: Innovation with Focus

Andes is a pure-play CPU IP provider with a broad impact across the semiconductor landscape. With deep engagement in safety-certified applications, artificial intelligence, and cloud-edge computing convergence, the company is well poised to shape the future of RISC-V in markets that demand both performance and trust.

To learn more, visit Andes website.

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