Arteris at the 2025 Design Automation Conference #62DAC

Key Takeaways:

• Expanded Multi-Die Solution: Arteris showcases its foundational technology for rapid chiplet-based innovation. Check out the multi-die highlights video.
• Ecosystem compatibility: Supported through integration with products from major EDA and foundry partners, including Cadence, Synopsys, and global semiconductor fabs.
• Optimized SoC Integration: Magillem Connectivity automates assembly from IP and chiplets, reducing risks associated with manual, error-prone tasks.
• Consistent HW/SW Development: Magillem Registers automates integration from system map definition to validation and documentation, ensuring alignment through a single source of truth.
• Unified Interconnect IP: FlexGen, FlexNoC, and Ncore work together to manage coherent and non-coherent data flow across dies, enabling seamless multi-die integration.
• Live at Booth #2529: Meet Arteris experts at DAC 2025 to learn how its silicon-proven technologies accelerate multi-die SoC design.
• Presentation at EETimes Chiplet Pavilion: Join Arteris product experts on Tuesday, June 24^th, at 4:15 p.m. in the Chiplet Pavilion Booth #2308 for “Chiplets: Opportunities and Challenges.”

Read the latest Arteris SemiWiki blog: Arteris Expands Their Multi-Die Support – SemiWiki

Arteris, a leading provider of system IP, recently announced an expansion of its multi-die solution and will showcase its latest technology, including network-on-chip (NoC) interconnect IP and SoC integration automation solutions providing foundational technology for chiplet-based innovation.

The company offers a product portfolio that supports interoperability and efficient communication among disparate chiplets, streamlining integration across a broad range of implementations. Their recently expanded solution enables multi-die systems to operate as a unified platform that appears monolithic to software developers.

Magillem Connectivity

Magillem Connectivity provides optimized automation for SoC assembly from IP blocks and chiplets. It reduces project risks by eliminating manual, error-prone integration tasks. Based on the IEEE 1685 (IP-XACT) standard, it enables hierarchical integration views, consistent interface definitions, and system-level connectivity. In multi-die systems, it coordinates the integration process across dies, improving design accuracy and accelerating assembly.

Magillem Registers

Magillem Registers delivers optimized automation for integrating hardware and software from system map definition to validation and documentation. It operates from a single source of truth to ensure consistency and traceability across the development flow. The tool automates the management of control and status registers and supports multi-die environments by synchronizing register specifications across dies to streamline hardware/software integration.

FlexGen Interconnect IP

FlexGen is a highly configurable, smart interconnect IP that supports a wide range of protocols and traffic types. It enables flexible topology generation and protocol-aware integration, helping accelerate system design. Using industry standard protocols such as AMBA, FlexGen supports integration with third-party die-to-die controllers and PHYs through standard interfaces.

FlexNoC Non-Coherent Interconnect IP

FlexNoC shares a common subset of features with FlexGen, enabling manual NoC configuration, and is used widely in AI chiplet-based designs today.

Ncore Cache Coherent Interconnect IP

Ncore enables seamless cache coherent reads and writes across chiplets, allowing multi-die systems to behave as a unified platform. It supports standard protocols including CHI and ACE, ensuring correct memory ordering and coherent communication between CPUs, GPUs, and accelerators. Ncore is designed for scalability, low latency, and functional safety with ISO 26262 certification.

Arteris invites you to meet the team at booth #2529 at DAC 2025.

To learn more about Arteris, visit www.arteris.com.