Xilinx’s 16nm UltraScale+ FPGA is Revolutionary

Well a very belated Happy New Year dear reader. I must admit, it has been a very long winter and it has caused the Miller’s to rethink this vital question. “What in the world are we doing living in NY”. So we are moving, and hopefully this is my last ‘real’ winter as we headed down south. To perhaps alleviate some of the winter blues from you a bit I see Xilinx has released their16nm UltraScale+ Product Tables. You can read them here.

While much of the news and attention is on the MPSoC and the VU13P that has like near ~12,000 DSP, 128 30g SERDES, ~500Mb RAM and the kitchen sink. I really could put a complete RADAR on that chip, Amazing! Just study this figure for a few minutes.

Being a Xilinx employee I can personally attest that these parts were intelligently designed, no evolution here. There was many, many hours of hard work across all disciplines to create these FPGAs. I personally like working for Xilinx for that reason, you can participate in the product of hard team work. Then to see the FPGAs working in real systems, at the least is very satisfying. Almost like watching a mom giving birth. (Believe that do you?) Miller #8 is expected end of March Lord Willing. I shall name him “Zynq MPSoC Miller”.

Over the last few months, I heckled Xilinx via email, nicely of course, “hey can I leak just a little bit about the 16nm FPGAs?” I mean they were great written emails, proof read by the wife. I eagerly awaited my response which was ‘No’. I understood, but boy the suspense was killing me but after some patience testing, this was the week. My kids were as excited as Christmas Day. Xilinx revealed what was in store at 16nm. By me not being ‘leaky’ prevented any type of miscommunication.

Speaking of miscommunication, this is a REAL conversation I had with the wife, really. Can any of you readers of the male persuasion relate here?

• Luke: “I’m going out, do you need me to pick up anything.” (Safe question, and necessary, 50 points)
• Wife: “Well, we are out of hamburger, so do not get that.”
• Luke: “huh” …(With a very complicated look on my face)

Now in ‘marriage conversation’, I believe the Lorenz dilation does in fact take place and hours go by when talking with the wife on such subjects. Men speak blue, Women pink. Please translate accordingly. Can any of you guess what she really meant?

Back to Xilinx but I needed to get that off my chest.

At 16nm remember this phrase “Tools, Tools, Tools”. I must admit you simply cannot just pick up one of these devices and start coding blindly. It is now about Tools and Architecture. The MPSoC, has ARMs, Legs, R5’s, GPU, H.264/265 , Power Management and Programmable Logic. I believe it is the time to embrace across team disciplines (systems, software, and hardware) and High Level Synthesis. You cannot simply be competitive and program these puppies by hand. C/C++, OpenCL are the key to stay portable and to keep from wheel spinning. Xilinx Vivado HLS will give you better QoR (Smaller, Faster, Denser designs).

What does 12,000 DSP and 128, 30g SERDES give you. About 20 TMACs of processing power and a plethora of options to all the revolutionary serial standards like JESD204b (c is chartering out) and Hybrid Memory Cube. Friend DDR has died, and I believe we are about to witness the death of wide LVDS ADC/DAC devices soon when lower latency is achieved in the JESD204 devices. This is why you need 128 GTs. Five years ago you probably did not. A 32 channel RADAR receiver is cake in such a part. 30g is all important. The next gen HMC, and JESD204 will need that rate, 28g will not cut it. What should you do next? Read ALL the materials which Xilinx has posted. Contact you sales rep and get more info. Get a 16nm evaluation board when available. You simply cannot beat having a fully working framework ready to go. Get HLS training, Start C/C++, OpenCL coding. Get Vivado training and for goodness sake stay warm and safe the rest of this winter!