Top 10 Reasons to Use Vivado Design Suite

Here are the top 10 reasons to use the Xilinx Vivado Design Suite to design your All Programmable Devices:

Reason number 10: Accelerate verification by over 100XThe Vivado Design Suite System Edition lets you do design at the C, C++ or systemC level. But a side-benefit is that you can use these languages for verification at performances much higher than using raw RTL. Maybe 10,000X faster.

Reason number 9: Comprehensive hardware debugVivado Design Suite’s probing methodologies are intuitive and flexible. Designers can choose a strategy that best suits their design flow using RTL design files, synthesized design and XDC constraint file. Or netlist insertion. Or interactive Tcl or scripts to automate probing.

Reason number 8: Vivado IDE for design and simulationThere is a complete, fully-integrated set of tools for design entry, timing analysis, hardware debug and simulation encapsulated in a state of the art integrated design environment (IDE).

Reason number 7: Block based IP integrationVivado IP integrator is the industry’s first plug-and-play IP integration design environment. This provides a graphical and Tcl based correct-by-construction design flow.

Reason number 6: Model-based DSP design integrationUsing System Generator for DSP, the industry’s leading high-level design tool for converting DSP algorithms into production quality hardware. It interfaces to the industry’s quasi-standard modeling tools, MATLAB and Simulink (from Mathworks).

Reason number 5: High level synthesisVivado High Level Synthesis takes C, C++ and SystemC and automatically converts it into Verilog or VHDL for further synthesis. This previously somewhat esoteric technology is now completely mainstream with hundreds of users.

Reason number 4: Performance, performance, performanceMuch faster run-time than the competition. Multiple compilations per day even on huge designs. Much smaller memory footprint than the competition.

Reason number 3: Robust performance and low powerInterconnect is now the performance bottleneck in modern programmable-logic devices. The place & route algorithms in Vivado break this performance bottleneck to deliver high performance results at the push of a button. Higher performance than the competition. It also delivers lower system power.

Reason number 2: Fit more into the device, fasterA tool’s ability to fit more functions into an All Programmable device directly translates into savings in system-level cost and power by letting you select the smallest device for your design. The advanced fitting algorithms combined with the architecture of the Xilinx 7 devices allow nearly 100% utilization to be achieved whereas competing devices on the same benchmark top out at 67%, meaning a larger and more expensive device would be required.

And the number 1 reason for using Vivado Design Suite:That is how you get your hands on Xilinx’s All Programmable devices. Because like in those old Visa ads, they don’t take American Express.

A full white-paper that dives deeper into each of these reasons is available here.

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