Structured Asic Dies…Again

There has always been a dream that you could do a design in a cheap easy to design technology and then, if the design was a hit, press a button and instantly move it into a cheaper unit-price high volume design. When I was at VLSI in the 1980s we had approaches to make it easy to move gate arrays (relatively large die area) into standard cells almost automatically. Another approach was to try and get the design cost down and find a sweet spot between FPGAs and SoCs. LSI Logic had RapidChip structured-ASIC starting in the early 2000s, with pre-configured IP blocks and platforms that could quickly be programmed with just metal. Neither was successful.

This was especially attractive to FPGA vendors. By their nature, FPGAs are not very efficient in their use of silicon and so FPGA vendors such as Xilinx and Altera felt under pressure that if designs went into high volume manufacturing (HVM) that they should have a way to get the design into something more silicon efficient so they didn’t lose the customer. Xilinx had a program called HardWire to do just this but it was killed off over a decade ago. Apparently they didn’t lose the customers without such a program.

Altera had a program called HardCopy, When John Daane first joined Altera as CEO he was very bullish about the role that HardCopy would have in Altera’s success and expected it to be a critical differentiator. He expected HardCopy would be 10% of their revenues by 2004. They even had a program called SiliconPro that was basically design services: take the netlist from the FPGA and do a full implementation using standard-cells. They hired a group in Penang to support all these HardCopy designs but…they never materialized. By 2004 HardCopy was 1-2% of Altera’s revenue and maybe got as high as 5% in the end.

And when I say in the end, that’s what I mean. Altera quietly dropped it from their product line:

“Altera no longer offers HardCopy structured ASIC products for new design starts”

Years ago, when I was at Ambit I think, I talked to the team that designed the Rio. This was the first (or the first reasonably successful) portable mp3 player, an iPod long before iPods. It was FPGA-based. I asked them why when it took off they didn’t immediately do a much-lower unit cost cell-based version. He told me that he could do one of two things with his design team. Cost-reduce the current Rio, or do a new FPGA-based Rio2. No prizes for guessing which option they chose. That is the heart of the problem.

Another problem is that if Rio did produce the ultimate standard product for implementing mp3 players (let’s call it PortalPlayer just for fun) then why would they not want to make as much money as possible selling the chips to everyone (such as, say, Apple) rather than selling mp3 players. Eventually other companies would produce ASSPs in the space and Rio could use them (because if they didn’t their competitors would probably undercut them).

The reality is that there seems to be a space for doing quick and easy designs even if the unit cost is high (FPGAs). Get to market fast, get traction. And there is a space for doing complex standard products that are sold to the general market. There is not a space for doing moderately hard designs at a moderately low unit price, especially if the volumes are low, nor for semi-automatically moving designs up the chain. It just doesn’t work smoothly enough and the next generation design is always more important than cost-reducing the last one.

Apple is rich enough that they can bridge the strategy: expensive designs that they do not sell to the general market, a strategy that wouldn’t have worked for the much smaller Rio. But even they buy their modems from Qualcomm. And A7 is not a cost-reduced A6: it is the next generation.

I think by now it is safe to say that there isn’t really a sweet-spot between FPGAs and SoCs. As in products from Xilinx (I know they will tell you they do much more than FPGAs these days, and they do) and products from Qualcomm/Broadcom/etc. It is the comparison in design methodology that is probably key: the FPGA methodology is fairly automatic, SoC requires $100Ms in design tools and the best designers in the world. There isn’t a gap in between.

More details on Xilinx UltraScale are here.

More articles by Paul McLellan…