Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)
- Thread starter Daniel Nenni
- Start date
UMC is a teaching partner.
I do not believe TSMC works with PDF internally. UMC used to for sure as it is all about yield. A partnership with PDF is a good thing for Intel Foundry, absolutely.
Yes. Sassine emphasize it is synopsys when he started speaking.Did you notice that Lip-Bu called him Sassine Gaza CEO of Cadence?
Perhaps LipBu knows something we don't
I guess 10 years of leading cadence have that imprinted in LipBu mind deeply.
It is interesting to note that Intel will have two versions of 14A, EUV and HNA-EUV. My guess is that HNA-EUV will not have the throughput for HVM in that time frame so Intel can use HNA-UEV for internal products while offering 14 EUV for customers. Since TSMC A16 and A14 are EUV this should not be a competitive problem for IFS.
MKWVentures
Moderator
Great Info thanks
18A high volume in Q4 2025, correct? any idea how high the volume is? 10K per month?
So the Tapeouts to date on 18A are Government? those are actual products Taped out already?
18A high volume in Q4 2025, correct? any idea how high the volume is? 10K per month?
So the Tapeouts to date on 18A are Government? those are actual products Taped out already?
Yes. Sassine emphasize it is synopsys when he started speaking.
Perhaps LipBu knows something we don't
No, the only IFS tape-out to date is MediaTek. The US Government will use 18A for AI chips is my guess but that will be 18AP. I'm wondering how many 18A customers will push it out to 18AP for the extra performance? Intel 18AP was due to customer demand, right?
Is it really necessary to call Intel the "embattled chipmaker"? How low can Reuters go?
By Max A. Cherney, Stephen Nellis
SAN JOSE, California (Reuters) -Intel said on Tuesday that several of its contract manufacturing customers planned to build test chips for a forthcoming advanced manufacturing process, which the company still has in development.
The embattled chipmaker indicated it had received interest from customers at its Direct Connect conference on Tuesday for its contract chip business, or foundry. Intel's attempt to build a foundry unit has hit snags, but ultimately the goal has been to rival TSMC.
By Max A. Cherney, Stephen Nellis
SAN JOSE, California (Reuters) -Intel said on Tuesday that several of its contract manufacturing customers planned to build test chips for a forthcoming advanced manufacturing process, which the company still has in development.
The embattled chipmaker indicated it had received interest from customers at its Direct Connect conference on Tuesday for its contract chip business, or foundry. Intel's attempt to build a foundry unit has hit snags, but ultimately the goal has been to rival TSMC.
hist78
Well-known member
To make matters even more confusing, Apple iPhones utilize the Apple A* series SoCs. The iPhone 16 Pro and Pro Max, released in 2024, are powered by the Apple A18 and A18 Pro SoCs, which were designed by Apple and manufactured using TSMC's N3E process.
The Apple A18 outperforms the A17, which in turn surpasses the A16, A15, and A14. Based on Apple’s naming convention, a larger number indicates a more advanced and powerful SoC compared to those with smaller numbers while TSMC is going the opposite way.
Additionally, it’s possible that we may soon see Apple A21 SoCs manufactured using TSMC's A14 process and Apple A23 SoCs produced with TSMC's A10 process. This naming evolution seems confusing between Apple and TSMC.
jorgequinonez
Member
Thank Apple too for their uncreative AP names (A17, A18, A19....).
siliconbruh999
Well-known member
This news is over a year old. Intel has mentioned that which one they use will depend on which one is better almost a half dozen times at this point. Parallel developments and derisking high risk items were two of the things Ann K said she changed about how Intel does development during interviews she has done over the years.
I don't think so. The pre-production high-NA tools are faster at the same dose than those early low-NA tools were, and production models will be even faster. If we ignore that and say they will be the same productivity. Taking TSMC N7 as an example. Back in 2019 when they started iphone and Huawei SOC production on N7+, they had less than 20 tools between N5 risk production, N7+ HVM, and R&D. I think techinshights thought the number was in the single digits dedicated for N7+ HVM. TSMC N7+ was using 4 layers and N6 was using like 6-8 layers. If we say that modern Intel ramp is 1/2 the size of modern TSMC ramp then if 14A uses a similar amount of high-NA to N7+ or N6 then Intel doesn't need many tools for HVM. If they do, like 8 layers of high-NA at half the volume of modern TSMC, we are talking single digit tool counts. Even if Intel is doing something like an N5 level of all in like I don't know 14 layers (1 layer per angstrom
) we are still talking about low-mid 10s. Even getting 10 tools over the next 2 years is not exactly a big ask when ASML supposedly made 10 last year. For TSMC, it is harder, but it can't be that hard. TSMC is starting HVM in 2028 for Apple with A14A starting in 2029. So even in we say 20 tools with maybe 10-15 installed/qual'd by EOY 2029 and the other 5-10 installed/qual'd by EOY 2030. In this scenarios' worst case, we are talking about TSMC getting 15 tools over the next 4 years (on average, less than 4 units per year from here on out). I just don't really see the evidence that high-NA rollouts are being delayed due to insufficient capacity when I reference to do the low-NA rollout. And realistically it should go faster than that since high-NA is evolutionary rather than revolutionary.From what I've heard, they do. But that is third hand information, so I could be wrong.
I think it is a mistake, they weren't working together even before Intel started on their foundry endeavors. My understanding is that be it an IDM or a foundry, people use PDF because their services/ability to put your process through its paces have no match. Back in the old days sure not needed. In this era with complex design process interactions, and the minefield of LLEs just waiting to blow off your leg you MUST understand where the process corners are.
Yup, if we are talking about final product and not customer or ecosystem testchips, and if we don't count advanced packaging tapeouts (which I wouldn't count) then just Mediatek for now. Tower mentioned they were starting up 65nm in NM, but I don't count that as a tapeout since Tower is just using Intel as cheap (because it is 300mm) second source capacity. Intel 3 customer has not annouced a final product tapeout yet, and the first foundry customer on 18A is slated to tapeout real products in 2H25.
I don't really think you need to push to do that. Intel is going to 18A-P production next year and the very first external tapeout for 18A isn't until EOY2025 due to foundry readiness trailing process readiness by 6-12mo. Using 18A-P lines up with the schedule for people anyways. Kind of like TSMC P nodes. People don't push products out to use the P version. That is just what is available when people start running their TSMC products (Apple of course being the exception).
I mean probably not totally. Intel products was always going to want a + version with even more performance. But the extra VTs, smoother process corners, lower variation, lower Vmin, lower leakage, etc. Intel says are because external customers asked for them. I don't know why anyone would ever lie about something like that, so I would assume that part is true.
That isn't really news either. Intel said Intel 4+powerVia was cost neutral. It is also well documented by semiconductor makers, IMEC, and tool vendor research that BSPDNs are a requirement to continued cost-effective scaling. FSPDN first process technologies are an evolutionary dead end (just like the 22/20nm planar devices of old).
Last edited:
Mostly themselves and what a great partner Intel is. These events are mostly canned but it is good to see old friends and make new ones.
So are they going to consider using Intel Foundry?